shylie/llvm-project

History

Peiming Liu 07bf1ddb4e

[mlir][sparse] support non-id map for [Dis]assembleOp (#80355 )

2024-02-01 15:11:33 -08:00

..

benchmark/python

[mlir][benchmark] Fix broken benchmark script (#68841 )

2023-12-06 12:17:53 +05:30

Revert "[mlir] Consider mlir-linalg-ods-gen as a tablegen tool in build (#75093 )"

2024-01-04 02:01:16 +05:00

[mlir][mesh] Refactoring code organization, tests and docs (#79606 )

2024-01-31 07:20:14 -08:00

[mlir][IR] Rename "update root" to "modify op" in rewriter API (#78260 )

2024-01-17 11:08:59 +01:00

[mlir][sparse] external entry method wrapper for sparse tensors (#80326 )

2024-02-01 13:32:52 -08:00

[mlir][sparse] support non-id map for [Dis]assembleOp (#80355 )

2024-02-01 15:11:33 -08:00

[mlir][python] enable memref.subview (#79393 )

2024-01-30 16:21:56 -06:00

[mlir][sparse] support non-id map for [Dis]assembleOp (#80355 )

2024-02-01 15:11:33 -08:00

[llvm] Move CodeGenTypes library to its own directory (#79444 )

2024-01-25 12:01:31 -05:00

[mlir][openacc][flang] Support wait devnum and clean async/wait IR (#79525 )

2024-01-28 21:17:36 -08:00

[emacs] Fix Emacs library formatting (#76110 )

2024-01-10 13:14:21 +01:00

.clang-format

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.clang-tidy

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CMakeLists.txt

[mlir] Add config for PDL (#69927 )

2024-01-03 20:37:20 -08:00

LICENSE.TXT

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README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.