aba3476111
This is split off from #71764, and moves only the vmv.v.v part of performCombineVMergeAndVOps to work on MachineInstrs. In retrospect trying to handle PseudoVMV_V_V and PseudoVMERGE_VVM in the same function makes the code quite hard to read, so this just does it in a separate peephole. This turns out to be simpler since for PseudoVMV_V_V we don't need to convert the Src instruction to a masked variant, and we don't need to create a fake all ones mask.
514 lines
18 KiB
C++
514 lines
18 KiB
C++
//===- RISCVVectorPeephole.cpp - MI Vector Pseudo Peepholes ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs various vector pseudo peephole optimisations after
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// instruction selection.
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//
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// Currently it converts vmerge.vvm to vmv.v.v
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// PseudoVMERGE_VVM %false, %false, %true, %allonesmask, %vl, %sew
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// ->
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// PseudoVMV_V_V %false, %true, %vl, %sew
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//
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// And masked pseudos to unmasked pseudos
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// PseudoVADD_V_V_MASK %passthru, %a, %b, %allonesmask, %vl, sew, policy
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// ->
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// PseudoVADD_V_V %passthru %a, %b, %vl, sew, policy
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//
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// It also converts AVLs to VLMAX where possible
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// %vl = VLENB * something
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// PseudoVADD_V_V %passthru, %a, %b, %vl, sew, policy
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// ->
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// PseudoVADD_V_V %passthru, %a, %b, -1, sew, policy
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVISelDAGToDAG.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-vector-peephole"
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namespace {
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class RISCVVectorPeephole : public MachineFunctionPass {
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public:
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static char ID;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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const RISCVSubtarget *ST;
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RISCVVectorPeephole() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::IsSSA);
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}
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StringRef getPassName() const override {
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return "RISC-V Vector Peephole Optimization";
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}
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private:
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bool convertToVLMAX(MachineInstr &MI) const;
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bool convertToWholeRegister(MachineInstr &MI) const;
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bool convertToUnmasked(MachineInstr &MI) const;
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bool convertVMergeToVMv(MachineInstr &MI) const;
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bool foldVMV_V_V(MachineInstr &MI);
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bool isAllOnesMask(const MachineInstr *MaskDef) const;
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std::optional<unsigned> getConstant(const MachineOperand &VL) const;
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/// Maps uses of V0 to the corresponding def of V0.
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DenseMap<const MachineInstr *, const MachineInstr *> V0Defs;
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};
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} // namespace
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char RISCVVectorPeephole::ID = 0;
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INITIALIZE_PASS(RISCVVectorPeephole, DEBUG_TYPE, "RISC-V Fold Masks", false,
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false)
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/// Check if an operand is an immediate or a materialized ADDI $x0, imm.
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std::optional<unsigned>
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RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
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if (VL.isImm())
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return VL.getImm();
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MachineInstr *Def = MRI->getVRegDef(VL.getReg());
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if (!Def || Def->getOpcode() != RISCV::ADDI ||
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Def->getOperand(1).getReg() != RISCV::X0)
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return std::nullopt;
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return Def->getOperand(2).getImm();
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}
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/// Convert AVLs that are known to be VLMAX to the VLMAX sentinel.
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bool RISCVVectorPeephole::convertToVLMAX(MachineInstr &MI) const {
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if (!RISCVII::hasVLOp(MI.getDesc().TSFlags) ||
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!RISCVII::hasSEWOp(MI.getDesc().TSFlags))
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return false;
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auto LMUL = RISCVVType::decodeVLMUL(RISCVII::getLMul(MI.getDesc().TSFlags));
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// Fixed-point value, denominator=8
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unsigned LMULFixed = LMUL.second ? (8 / LMUL.first) : 8 * LMUL.first;
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unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
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// A Log2SEW of 0 is an operation on mask registers only
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unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
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assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
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assert(8 * LMULFixed / SEW > 0);
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// If the exact VLEN is known then we know VLMAX, check if the AVL == VLMAX.
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MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
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if (auto VLen = ST->getRealVLen(), AVL = getConstant(VL);
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VLen && AVL && (*VLen * LMULFixed) / SEW == *AVL * 8) {
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VL.ChangeToImmediate(RISCV::VLMaxSentinel);
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return true;
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}
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// If an AVL is a VLENB that's possibly scaled to be equal to VLMAX, convert
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// it to the VLMAX sentinel value.
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if (!VL.isReg())
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return false;
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MachineInstr *Def = MRI->getVRegDef(VL.getReg());
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if (!Def)
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return false;
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// Fixed-point value, denominator=8
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uint64_t ScaleFixed = 8;
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// Check if the VLENB was potentially scaled with slli/srli
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if (Def->getOpcode() == RISCV::SLLI) {
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assert(Def->getOperand(2).getImm() < 64);
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ScaleFixed <<= Def->getOperand(2).getImm();
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Def = MRI->getVRegDef(Def->getOperand(1).getReg());
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} else if (Def->getOpcode() == RISCV::SRLI) {
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assert(Def->getOperand(2).getImm() < 64);
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ScaleFixed >>= Def->getOperand(2).getImm();
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Def = MRI->getVRegDef(Def->getOperand(1).getReg());
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}
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if (!Def || Def->getOpcode() != RISCV::PseudoReadVLENB)
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return false;
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// AVL = (VLENB * Scale)
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//
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// VLMAX = (VLENB * 8 * LMUL) / SEW
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//
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// AVL == VLMAX
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// -> VLENB * Scale == (VLENB * 8 * LMUL) / SEW
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// -> Scale == (8 * LMUL) / SEW
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if (ScaleFixed != 8 * LMULFixed / SEW)
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return false;
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VL.ChangeToImmediate(RISCV::VLMaxSentinel);
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return true;
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}
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bool RISCVVectorPeephole::isAllOnesMask(const MachineInstr *MaskDef) const {
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assert(MaskDef && MaskDef->isCopy() &&
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MaskDef->getOperand(0).getReg() == RISCV::V0);
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Register SrcReg = TRI->lookThruCopyLike(MaskDef->getOperand(1).getReg(), MRI);
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if (!SrcReg.isVirtual())
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return false;
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MaskDef = MRI->getVRegDef(SrcReg);
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if (!MaskDef)
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return false;
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// TODO: Check that the VMSET is the expected bitwidth? The pseudo has
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// undefined behaviour if it's the wrong bitwidth, so we could choose to
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// assume that it's all-ones? Same applies to its VL.
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switch (MaskDef->getOpcode()) {
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case RISCV::PseudoVMSET_M_B1:
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case RISCV::PseudoVMSET_M_B2:
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case RISCV::PseudoVMSET_M_B4:
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case RISCV::PseudoVMSET_M_B8:
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case RISCV::PseudoVMSET_M_B16:
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case RISCV::PseudoVMSET_M_B32:
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case RISCV::PseudoVMSET_M_B64:
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return true;
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default:
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return false;
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}
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}
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/// Convert unit strided unmasked loads and stores to whole-register equivalents
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/// to avoid the dependency on $vl and $vtype.
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///
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/// %x = PseudoVLE8_V_M1 %passthru, %ptr, %vlmax, policy
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/// PseudoVSE8_V_M1 %v, %ptr, %vlmax
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///
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/// ->
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///
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/// %x = VL1RE8_V %ptr
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/// VS1R_V %v, %ptr
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bool RISCVVectorPeephole::convertToWholeRegister(MachineInstr &MI) const {
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#define CASE_WHOLE_REGISTER_LMUL_SEW(lmul, sew) \
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case RISCV::PseudoVLE##sew##_V_M##lmul: \
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NewOpc = RISCV::VL##lmul##RE##sew##_V; \
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break; \
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case RISCV::PseudoVSE##sew##_V_M##lmul: \
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NewOpc = RISCV::VS##lmul##R_V; \
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break;
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#define CASE_WHOLE_REGISTER_LMUL(lmul) \
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CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 8) \
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CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 16) \
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CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 32) \
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CASE_WHOLE_REGISTER_LMUL_SEW(lmul, 64)
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unsigned NewOpc;
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switch (MI.getOpcode()) {
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CASE_WHOLE_REGISTER_LMUL(1)
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CASE_WHOLE_REGISTER_LMUL(2)
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CASE_WHOLE_REGISTER_LMUL(4)
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CASE_WHOLE_REGISTER_LMUL(8)
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default:
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return false;
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}
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MachineOperand &VLOp = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
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if (!VLOp.isImm() || VLOp.getImm() != RISCV::VLMaxSentinel)
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return false;
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// Whole register instructions aren't pseudos so they don't have
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// policy/SEW/AVL ops, and they don't have passthrus.
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if (RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags))
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MI.removeOperand(RISCVII::getVecPolicyOpNum(MI.getDesc()));
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MI.removeOperand(RISCVII::getSEWOpNum(MI.getDesc()));
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MI.removeOperand(RISCVII::getVLOpNum(MI.getDesc()));
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if (RISCVII::isFirstDefTiedToFirstUse(MI.getDesc()))
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MI.removeOperand(1);
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MI.setDesc(TII->get(NewOpc));
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return true;
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}
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// Transform (VMERGE_VVM_<LMUL> false, false, true, allones, vl, sew) to
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// (VMV_V_V_<LMUL> false, true, vl, sew). It may decrease uses of VMSET.
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bool RISCVVectorPeephole::convertVMergeToVMv(MachineInstr &MI) const {
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#define CASE_VMERGE_TO_VMV(lmul) \
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case RISCV::PseudoVMERGE_VVM_##lmul: \
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NewOpc = RISCV::PseudoVMV_V_V_##lmul; \
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break;
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unsigned NewOpc;
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switch (MI.getOpcode()) {
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default:
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return false;
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CASE_VMERGE_TO_VMV(MF8)
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CASE_VMERGE_TO_VMV(MF4)
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CASE_VMERGE_TO_VMV(MF2)
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CASE_VMERGE_TO_VMV(M1)
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CASE_VMERGE_TO_VMV(M2)
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CASE_VMERGE_TO_VMV(M4)
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CASE_VMERGE_TO_VMV(M8)
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}
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Register PassthruReg = MI.getOperand(1).getReg();
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Register FalseReg = MI.getOperand(2).getReg();
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// Check passthru == false (or passthru == undef)
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if (PassthruReg != RISCV::NoRegister &&
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TRI->lookThruCopyLike(PassthruReg, MRI) !=
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TRI->lookThruCopyLike(FalseReg, MRI))
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return false;
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assert(MI.getOperand(4).isReg() && MI.getOperand(4).getReg() == RISCV::V0);
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if (!isAllOnesMask(V0Defs.lookup(&MI)))
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return false;
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MI.setDesc(TII->get(NewOpc));
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MI.removeOperand(1); // Passthru operand
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MI.tieOperands(0, 1); // Tie false to dest
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MI.removeOperand(3); // Mask operand
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MI.addOperand(
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MachineOperand::CreateImm(RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED));
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// vmv.v.v doesn't have a mask operand, so we may be able to inflate the
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// register class for the destination and passthru operands e.g. VRNoV0 -> VR
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MRI->recomputeRegClass(MI.getOperand(0).getReg());
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MRI->recomputeRegClass(MI.getOperand(1).getReg());
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return true;
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}
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bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
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const RISCV::RISCVMaskedPseudoInfo *I =
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RISCV::getMaskedPseudoInfo(MI.getOpcode());
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if (!I)
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return false;
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if (!isAllOnesMask(V0Defs.lookup(&MI)))
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return false;
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// There are two classes of pseudos in the table - compares and
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// everything else. See the comment on RISCVMaskedPseudo for details.
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const unsigned Opc = I->UnmaskedPseudo;
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const MCInstrDesc &MCID = TII->get(Opc);
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[[maybe_unused]] const bool HasPolicyOp =
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RISCVII::hasVecPolicyOp(MCID.TSFlags);
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const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MCID);
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#ifndef NDEBUG
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const MCInstrDesc &MaskedMCID = TII->get(MI.getOpcode());
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assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ==
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RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
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"Masked and unmasked pseudos are inconsistent");
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assert(HasPolicyOp == HasPassthru && "Unexpected pseudo structure");
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#endif
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(void)HasPolicyOp;
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MI.setDesc(MCID);
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// TODO: Increment all MaskOpIdxs in tablegen by num of explicit defs?
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unsigned MaskOpIdx = I->MaskOpIdx + MI.getNumExplicitDefs();
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MI.removeOperand(MaskOpIdx);
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// The unmasked pseudo will no longer be constrained to the vrnov0 reg class,
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// so try and relax it to vr.
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MRI->recomputeRegClass(MI.getOperand(0).getReg());
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unsigned PassthruOpIdx = MI.getNumExplicitDefs();
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if (HasPassthru) {
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if (MI.getOperand(PassthruOpIdx).getReg() != RISCV::NoRegister)
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MRI->recomputeRegClass(MI.getOperand(PassthruOpIdx).getReg());
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} else
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MI.removeOperand(PassthruOpIdx);
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return true;
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}
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/// Given two VL operands, returns the one known to be the smallest or nullptr
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/// if unknown.
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static const MachineOperand *getKnownMinVL(const MachineOperand *LHS,
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const MachineOperand *RHS) {
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if (LHS->isReg() && RHS->isReg() && LHS->getReg().isVirtual() &&
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LHS->getReg() == RHS->getReg())
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return LHS;
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if (LHS->isImm() && LHS->getImm() == RISCV::VLMaxSentinel)
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return RHS;
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if (RHS->isImm() && RHS->getImm() == RISCV::VLMaxSentinel)
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return LHS;
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if (!LHS->isImm() || !RHS->isImm())
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return nullptr;
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return LHS->getImm() <= RHS->getImm() ? LHS : RHS;
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}
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/// Check if it's safe to move From down to To, checking that no physical
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/// registers are clobbered.
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static bool isSafeToMove(const MachineInstr &From, const MachineInstr &To) {
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assert(From.getParent() == To.getParent() && !From.hasImplicitDef());
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SmallVector<Register> PhysUses;
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for (const MachineOperand &MO : From.all_uses())
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if (MO.getReg().isPhysical())
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PhysUses.push_back(MO.getReg());
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bool SawStore = false;
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for (auto II = From.getIterator(); II != To.getIterator(); II++) {
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for (Register PhysReg : PhysUses)
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if (II->definesRegister(PhysReg, nullptr))
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return false;
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if (II->mayStore()) {
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SawStore = true;
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break;
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}
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}
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return From.isSafeToMove(SawStore);
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}
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static unsigned getSEWLMULRatio(const MachineInstr &MI) {
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RISCVII::VLMUL LMUL = RISCVII::getLMul(MI.getDesc().TSFlags);
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unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();
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return RISCVVType::getSEWLMULRatio(1 << Log2SEW, LMUL);
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}
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/// If a PseudoVMV_V_V is the only user of its input, fold its passthru and VL
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/// into it.
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///
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/// %x = PseudoVADD_V_V_M1 %passthru, %a, %b, %vl1, sew, policy
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/// %y = PseudoVMV_V_V_M1 %passthru, %x, %vl2, sew, policy
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///
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/// ->
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///
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/// %y = PseudoVADD_V_V_M1 %passthru, %a, %b, min(vl1, vl2), sew, policy
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bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
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if (RISCV::getRVVMCOpcode(MI.getOpcode()) != RISCV::VMV_V_V)
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return false;
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MachineOperand &Passthru = MI.getOperand(1);
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if (!MRI->hasOneUse(MI.getOperand(2).getReg()))
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return false;
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MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
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if (!Src || Src->hasUnmodeledSideEffects() ||
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Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
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!RISCVII::isFirstDefTiedToFirstUse(Src->getDesc()) ||
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!RISCVII::hasVLOp(Src->getDesc().TSFlags) ||
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!RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags))
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return false;
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// Src needs to have the same VLMAX as MI
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if (getSEWLMULRatio(MI) != getSEWLMULRatio(*Src))
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return false;
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// Src needs to have the same passthru as VMV_V_V
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MachineOperand &SrcPassthru = Src->getOperand(1);
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if (SrcPassthru.getReg() != RISCV::NoRegister &&
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SrcPassthru.getReg() != Passthru.getReg())
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return false;
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// Because Src and MI have the same passthru, we can use either AVL as long as
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// it's the smaller of the two.
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//
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// (src pt, ..., vl=5) x x x x x|. . .
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// (vmv.v.v pt, src, vl=3) x x x|. . . . .
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// ->
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// (src pt, ..., vl=3) x x x|. . . . .
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//
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// (src pt, ..., vl=3) x x x|. . . . .
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// (vmv.v.v pt, src, vl=6) x x x . . .|. .
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// ->
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// (src pt, ..., vl=3) x x x|. . . . .
|
|
MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
|
|
const MachineOperand *MinVL = getKnownMinVL(&MI.getOperand(3), &SrcVL);
|
|
if (!MinVL)
|
|
return false;
|
|
|
|
bool VLChanged = !MinVL->isIdenticalTo(SrcVL);
|
|
bool ActiveElementsAffectResult = RISCVII::activeElementsAffectResult(
|
|
TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
|
|
|
|
if (VLChanged && (ActiveElementsAffectResult || Src->mayRaiseFPException()))
|
|
return false;
|
|
|
|
// If Src ends up using MI's passthru/VL, move it so it can access it.
|
|
// TODO: We don't need to do this if they already dominate Src.
|
|
if (!SrcVL.isIdenticalTo(*MinVL) || !SrcPassthru.isIdenticalTo(Passthru)) {
|
|
if (!isSafeToMove(*Src, MI))
|
|
return false;
|
|
Src->moveBefore(&MI);
|
|
}
|
|
|
|
if (SrcPassthru.getReg() != Passthru.getReg()) {
|
|
SrcPassthru.setReg(Passthru.getReg());
|
|
// If Src is masked then its passthru needs to be in VRNoV0.
|
|
if (Passthru.getReg() != RISCV::NoRegister)
|
|
MRI->constrainRegClass(Passthru.getReg(),
|
|
TII->getRegClass(Src->getDesc(), 1, TRI,
|
|
*Src->getParent()->getParent()));
|
|
}
|
|
|
|
if (MinVL->isImm())
|
|
SrcVL.ChangeToImmediate(MinVL->getImm());
|
|
else if (MinVL->isReg())
|
|
SrcVL.ChangeToRegister(MinVL->getReg(), false);
|
|
|
|
// Use a conservative tu,mu policy, RISCVInsertVSETVLI will relax it if
|
|
// passthru is undef.
|
|
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc()))
|
|
.setImm(RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED);
|
|
|
|
MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
|
|
MI.eraseFromParent();
|
|
V0Defs.erase(&MI);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
|
|
if (skipFunction(MF.getFunction()))
|
|
return false;
|
|
|
|
// Skip if the vector extension is not enabled.
|
|
ST = &MF.getSubtarget<RISCVSubtarget>();
|
|
if (!ST->hasVInstructions())
|
|
return false;
|
|
|
|
TII = ST->getInstrInfo();
|
|
MRI = &MF.getRegInfo();
|
|
TRI = MRI->getTargetRegisterInfo();
|
|
|
|
bool Changed = false;
|
|
|
|
// Masked pseudos coming out of isel will have their mask operand in the form:
|
|
//
|
|
// $v0:vr = COPY %mask:vr
|
|
// %x:vr = Pseudo_MASK %a:vr, %b:br, $v0:vr
|
|
//
|
|
// Because $v0 isn't in SSA, keep track of its definition at each use so we
|
|
// can check mask operands.
|
|
for (const MachineBasicBlock &MBB : MF) {
|
|
const MachineInstr *CurrentV0Def = nullptr;
|
|
for (const MachineInstr &MI : MBB) {
|
|
if (MI.readsRegister(RISCV::V0, TRI))
|
|
V0Defs[&MI] = CurrentV0Def;
|
|
|
|
if (MI.definesRegister(RISCV::V0, TRI))
|
|
CurrentV0Def = &MI;
|
|
}
|
|
}
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : make_early_inc_range(MBB)) {
|
|
Changed |= convertToVLMAX(MI);
|
|
Changed |= convertToUnmasked(MI);
|
|
Changed |= convertToWholeRegister(MI);
|
|
Changed |= convertVMergeToVMv(MI);
|
|
Changed |= foldVMV_V_V(MI);
|
|
}
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
FunctionPass *llvm::createRISCVVectorPeepholePass() {
|
|
return new RISCVVectorPeephole();
|
|
}
|