08289ad13a
Span-dependent instructions on RISC-V interact in a complex manner with linker relaxation. The span-dependent assembler algorithm implemented in LLVM has to start with the smallest version of an instruction and then only make it larger, so we compress instructions before emitting them to the streamer. When the instruction is streamed, the information that the instruction (or rather, the fixup on the instruction) is linker relaxable must be accurate, even though the assembler relaxation process may transform a not-linker-relaxable instruction/fixup into one that that is linker relaxable, for instance `c.jal` becoming `qc.e.jal`, or `bne` getting turned into `beq; jal` (the `jal` is linker relaxable). In order for this to work, the following things have to happen: - Any instruction/fixup which might be relaxed to a linker-relaxable instruction/fixup, gets marked as `RelaxCandidate = true` in RISCVMCCodeEmitter. - In RISCVAsmBackend, when emitting the `R_RISCV_RELAX` relocation, we have to check that the relocation/fixup kind is one that may need a relax relocation, as well as that it is marked as linker relaxable (the latter will not be set if relaxation is disabled). - Linker Relaxable instructions streamed to a Relaxable fragment need to mark the fragment and its section as linker relaxable. I also added more debug output for Sections/Fixups which are marked Linker Relaxable. This results in more relocations, when these PC-relative fixups cross an instruction with a fixup that is resolved as not linker-relaxable but caused the fragment to be marked linker relaxable at streaming time (i.e. `c.j`). (cherry picked from commit 9e8f7acd2b3a71dad473565a6a6f3ba51a3e6bca) Fixes: #150071
742 lines
27 KiB
C++
742 lines
27 KiB
C++
//===-- RISCVMCCodeEmitter.cpp - Convert RISC-V code to machine code ------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCAsmInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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STATISTIC(MCNumFixups, "Number of MC fixups created");
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namespace {
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class RISCVMCCodeEmitter : public MCCodeEmitter {
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RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
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void operator=(const RISCVMCCodeEmitter &) = delete;
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MCContext &Ctx;
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MCInstrInfo const &MCII;
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public:
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RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
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: Ctx(ctx), MCII(MCII) {}
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~RISCVMCCodeEmitter() override = default;
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void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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void expandFunctionCall(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void expandTLSDESCCall(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void expandAddTPRel(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void expandLongCondBr(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void expandQCLongCondBrImm(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI, unsigned Size) const;
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/// TableGen'erated function for getting the binary encoding for an
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/// instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of operand. If the machine operand requires
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/// relocation, record the relocation and return zero.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint64_t getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint64_t getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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template <unsigned N>
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unsigned getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new RISCVMCCodeEmitter(Ctx, MCII);
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}
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static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
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const MCExpr *Value, uint16_t Kind) {
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bool PCRel = false;
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switch (Kind) {
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case ELF::R_RISCV_CALL_PLT:
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case RISCV::fixup_riscv_pcrel_hi20:
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case RISCV::fixup_riscv_pcrel_lo12_i:
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case RISCV::fixup_riscv_pcrel_lo12_s:
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case RISCV::fixup_riscv_jal:
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case RISCV::fixup_riscv_branch:
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case RISCV::fixup_riscv_rvc_jump:
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case RISCV::fixup_riscv_rvc_branch:
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case RISCV::fixup_riscv_call:
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case RISCV::fixup_riscv_call_plt:
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case RISCV::fixup_riscv_qc_e_branch:
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case RISCV::fixup_riscv_qc_e_call_plt:
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case RISCV::fixup_riscv_nds_branch_10:
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PCRel = true;
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}
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Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
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}
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// Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
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// relocation types. We expand those pseudo-instructions while encoding them,
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// meaning AUIPC and JALR won't go through RISC-V MC to MC compressed
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// instruction transformation. This is acceptable because AUIPC has no 16-bit
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// form and C_JALR has no immediate operand field. We let linker relaxation
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// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
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// chance to relax to JAL.
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// If the C extension is enabled, JAL has a chance relax to C_JAL.
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void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCInst TmpInst;
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MCOperand Func;
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MCRegister Ra;
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if (MI.getOpcode() == RISCV::PseudoTAIL) {
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Func = MI.getOperand(0);
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Ra = RISCVII::getTailExpandUseRegNo(STI.getFeatureBits());
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} else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
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Func = MI.getOperand(1);
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Ra = MI.getOperand(0).getReg();
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} else if (MI.getOpcode() == RISCV::PseudoCALL) {
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Func = MI.getOperand(0);
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Ra = RISCV::X1;
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} else if (MI.getOpcode() == RISCV::PseudoJump) {
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Func = MI.getOperand(1);
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Ra = MI.getOperand(0).getReg();
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}
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uint32_t Binary;
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assert(Func.isExpr() && "Expected expression");
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const MCExpr *CallExpr = Func.getExpr();
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// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
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TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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if (MI.getOpcode() == RISCV::PseudoTAIL ||
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MI.getOpcode() == RISCV::PseudoJump)
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// Emit JALR X0, Ra, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
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else
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// Emit JALR Ra, Ra, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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}
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void RISCVMCCodeEmitter::expandTLSDESCCall(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCOperand SrcSymbol = MI.getOperand(3);
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assert(SrcSymbol.isExpr() &&
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"Expected expression as first input to TLSDESCCALL");
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const auto *Expr = dyn_cast<MCSpecifierExpr>(SrcSymbol.getExpr());
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MCRegister Link = MI.getOperand(0).getReg();
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MCRegister Dest = MI.getOperand(1).getReg();
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int64_t Imm = MI.getOperand(2).getImm();
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addFixup(Fixups, 0, Expr, ELF::R_RISCV_TLSDESC_CALL);
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MCInst Call =
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MCInstBuilder(RISCV::JALR).addReg(Link).addReg(Dest).addImm(Imm);
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uint32_t Binary = getBinaryCodeForInstr(Call, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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}
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// Expand PseudoAddTPRel to a simple ADD with the correct relocation.
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void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCOperand DestReg = MI.getOperand(0);
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MCOperand SrcReg = MI.getOperand(1);
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MCOperand TPReg = MI.getOperand(2);
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assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
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"Expected thread pointer as second input to TP-relative add");
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MCOperand SrcSymbol = MI.getOperand(3);
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assert(SrcSymbol.isExpr() &&
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"Expected expression as third input to TP-relative add");
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const auto *Expr = dyn_cast<MCSpecifierExpr>(SrcSymbol.getExpr());
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assert(Expr && Expr->getSpecifier() == ELF::R_RISCV_TPREL_ADD &&
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"Expected tprel_add relocation on TP-relative symbol");
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addFixup(Fixups, 0, Expr, ELF::R_RISCV_TPREL_ADD);
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if (STI.hasFeature(RISCV::FeatureRelax))
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Fixups.back().setLinkerRelaxable();
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// Emit a normal ADD instruction with the given operands.
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MCInst TmpInst = MCInstBuilder(RISCV::ADD)
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.addOperand(DestReg)
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.addOperand(SrcReg)
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.addOperand(TPReg);
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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}
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static unsigned getInvertedBranchOp(unsigned BrOp) {
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switch (BrOp) {
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default:
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llvm_unreachable("Unexpected branch opcode!");
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case RISCV::PseudoLongBEQ:
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return RISCV::BNE;
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case RISCV::PseudoLongBNE:
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return RISCV::BEQ;
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case RISCV::PseudoLongBLT:
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return RISCV::BGE;
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case RISCV::PseudoLongBGE:
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return RISCV::BLT;
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case RISCV::PseudoLongBLTU:
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return RISCV::BGEU;
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case RISCV::PseudoLongBGEU:
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return RISCV::BLTU;
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case RISCV::PseudoLongQC_BEQI:
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return RISCV::QC_BNEI;
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case RISCV::PseudoLongQC_BNEI:
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return RISCV::QC_BEQI;
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case RISCV::PseudoLongQC_BLTI:
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return RISCV::QC_BGEI;
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case RISCV::PseudoLongQC_BGEI:
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return RISCV::QC_BLTI;
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case RISCV::PseudoLongQC_BLTUI:
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return RISCV::QC_BGEUI;
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case RISCV::PseudoLongQC_BGEUI:
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return RISCV::QC_BLTUI;
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case RISCV::PseudoLongQC_E_BEQI:
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return RISCV::QC_E_BNEI;
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case RISCV::PseudoLongQC_E_BNEI:
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return RISCV::QC_E_BEQI;
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case RISCV::PseudoLongQC_E_BLTI:
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return RISCV::QC_E_BGEI;
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case RISCV::PseudoLongQC_E_BGEI:
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return RISCV::QC_E_BLTI;
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case RISCV::PseudoLongQC_E_BLTUI:
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return RISCV::QC_E_BGEUI;
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case RISCV::PseudoLongQC_E_BGEUI:
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return RISCV::QC_E_BLTUI;
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}
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}
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// Expand PseudoLongBxx to an inverted conditional branch and an unconditional
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// jump.
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void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCRegister SrcReg1 = MI.getOperand(0).getReg();
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MCRegister SrcReg2 = MI.getOperand(1).getReg();
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MCOperand SrcSymbol = MI.getOperand(2);
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unsigned Opcode = MI.getOpcode();
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bool IsEqTest =
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Opcode == RISCV::PseudoLongBNE || Opcode == RISCV::PseudoLongBEQ;
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bool UseCompressedBr = false;
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if (IsEqTest && STI.hasFeature(RISCV::FeatureStdExtZca)) {
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if (RISCV::X8 <= SrcReg1.id() && SrcReg1.id() <= RISCV::X15 &&
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SrcReg2.id() == RISCV::X0) {
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UseCompressedBr = true;
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} else if (RISCV::X8 <= SrcReg2.id() && SrcReg2.id() <= RISCV::X15 &&
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SrcReg1.id() == RISCV::X0) {
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std::swap(SrcReg1, SrcReg2);
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UseCompressedBr = true;
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}
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}
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uint32_t Offset;
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if (UseCompressedBr) {
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unsigned InvOpc =
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Opcode == RISCV::PseudoLongBNE ? RISCV::C_BEQZ : RISCV::C_BNEZ;
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MCInst TmpInst = MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(6);
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uint16_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write<uint16_t>(CB, Binary, llvm::endianness::little);
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Offset = 2;
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} else {
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unsigned InvOpc = getInvertedBranchOp(Opcode);
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MCInst TmpInst =
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MCInstBuilder(InvOpc).addReg(SrcReg1).addReg(SrcReg2).addImm(8);
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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Offset = 4;
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}
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// Save the number fixups.
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size_t FixupStartIndex = Fixups.size();
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// Emit an unconditional jump to the destination.
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MCInst TmpInst =
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MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);
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uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(CB, Binary, llvm::endianness::little);
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// Drop any fixup added so we can add the correct one.
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Fixups.resize(FixupStartIndex);
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if (SrcSymbol.isExpr())
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addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
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}
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// Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an
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// unconditional jump.
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void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI,
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unsigned Size) const {
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MCRegister SrcReg1 = MI.getOperand(0).getReg();
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auto BrImm = MI.getOperand(1).getImm();
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MCOperand SrcSymbol = MI.getOperand(2);
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unsigned Opcode = MI.getOpcode();
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uint32_t Offset;
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unsigned InvOpc = getInvertedBranchOp(Opcode);
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// Emit inverted conditional branch with offset:
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// 8 (QC.BXXX(4) + JAL(4))
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// or
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// 10 (QC.E.BXXX(6) + JAL(4)).
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if (Size == 4) {
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MCInst TmpBr =
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MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(BrImm).addImm(8);
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uint32_t BrBinary = getBinaryCodeForInstr(TmpBr, Fixups, STI);
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support::endian::write(CB, BrBinary, llvm::endianness::little);
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} else {
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MCInst TmpBr =
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MCInstBuilder(InvOpc).addReg(SrcReg1).addImm(BrImm).addImm(10);
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uint64_t BrBinary =
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getBinaryCodeForInstr(TmpBr, Fixups, STI) & 0xffff'ffff'ffffu;
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SmallVector<char, 8> Encoding;
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support::endian::write(Encoding, BrBinary, llvm::endianness::little);
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assert(Encoding[6] == 0 && Encoding[7] == 0 &&
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"Unexpected encoding for 48-bit instruction");
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Encoding.truncate(6);
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CB.append(Encoding);
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}
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Offset = Size;
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// Save the number fixups.
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size_t FixupStartIndex = Fixups.size();
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// Emit an unconditional jump to the destination.
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MCInst TmpJ =
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MCInstBuilder(RISCV::JAL).addReg(RISCV::X0).addOperand(SrcSymbol);
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uint32_t JBinary = getBinaryCodeForInstr(TmpJ, Fixups, STI);
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support::endian::write(CB, JBinary, llvm::endianness::little);
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// Drop any fixup added so we can add the correct one.
|
|
Fixups.resize(FixupStartIndex);
|
|
if (SrcSymbol.isExpr())
|
|
addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal);
|
|
}
|
|
|
|
void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI,
|
|
SmallVectorImpl<char> &CB,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
// Get byte count of instruction.
|
|
unsigned Size = Desc.getSize();
|
|
|
|
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
|
|
// expanded instructions for each pseudo is correct in the Size field of the
|
|
// tablegen definition for the pseudo.
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
break;
|
|
case RISCV::PseudoCALLReg:
|
|
case RISCV::PseudoCALL:
|
|
case RISCV::PseudoTAIL:
|
|
case RISCV::PseudoJump:
|
|
expandFunctionCall(MI, CB, Fixups, STI);
|
|
MCNumEmitted += 2;
|
|
return;
|
|
case RISCV::PseudoAddTPRel:
|
|
expandAddTPRel(MI, CB, Fixups, STI);
|
|
MCNumEmitted += 1;
|
|
return;
|
|
case RISCV::PseudoLongBEQ:
|
|
case RISCV::PseudoLongBNE:
|
|
case RISCV::PseudoLongBLT:
|
|
case RISCV::PseudoLongBGE:
|
|
case RISCV::PseudoLongBLTU:
|
|
case RISCV::PseudoLongBGEU:
|
|
expandLongCondBr(MI, CB, Fixups, STI);
|
|
MCNumEmitted += 2;
|
|
return;
|
|
case RISCV::PseudoLongQC_BEQI:
|
|
case RISCV::PseudoLongQC_BNEI:
|
|
case RISCV::PseudoLongQC_BLTI:
|
|
case RISCV::PseudoLongQC_BGEI:
|
|
case RISCV::PseudoLongQC_BLTUI:
|
|
case RISCV::PseudoLongQC_BGEUI:
|
|
expandQCLongCondBrImm(MI, CB, Fixups, STI, 4);
|
|
MCNumEmitted += 2;
|
|
return;
|
|
case RISCV::PseudoLongQC_E_BEQI:
|
|
case RISCV::PseudoLongQC_E_BNEI:
|
|
case RISCV::PseudoLongQC_E_BLTI:
|
|
case RISCV::PseudoLongQC_E_BGEI:
|
|
case RISCV::PseudoLongQC_E_BLTUI:
|
|
case RISCV::PseudoLongQC_E_BGEUI:
|
|
expandQCLongCondBrImm(MI, CB, Fixups, STI, 6);
|
|
MCNumEmitted += 2;
|
|
return;
|
|
case RISCV::PseudoTLSDESCCall:
|
|
expandTLSDESCCall(MI, CB, Fixups, STI);
|
|
MCNumEmitted += 1;
|
|
return;
|
|
}
|
|
|
|
switch (Size) {
|
|
default:
|
|
llvm_unreachable("Unhandled encodeInstruction length!");
|
|
case 2: {
|
|
uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
|
support::endian::write<uint16_t>(CB, Bits, llvm::endianness::little);
|
|
break;
|
|
}
|
|
case 4: {
|
|
uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
|
support::endian::write(CB, Bits, llvm::endianness::little);
|
|
break;
|
|
}
|
|
case 6: {
|
|
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI) & 0xffff'ffff'ffffu;
|
|
SmallVector<char, 8> Encoding;
|
|
support::endian::write(Encoding, Bits, llvm::endianness::little);
|
|
assert(Encoding[6] == 0 && Encoding[7] == 0 &&
|
|
"Unexpected encoding for 48-bit instruction");
|
|
Encoding.truncate(6);
|
|
CB.append(Encoding);
|
|
break;
|
|
}
|
|
case 8: {
|
|
uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
|
|
support::endian::write(CB, Bits, llvm::endianness::little);
|
|
break;
|
|
}
|
|
}
|
|
|
|
++MCNumEmitted; // Keep track of the # of mi's emitted.
|
|
}
|
|
|
|
uint64_t
|
|
RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
|
|
if (MO.isReg())
|
|
return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
|
|
|
|
if (MO.isImm())
|
|
return MO.getImm();
|
|
|
|
llvm_unreachable("Unhandled expression!");
|
|
return 0;
|
|
}
|
|
|
|
uint64_t
|
|
RISCVMCCodeEmitter::getImmOpValueMinus1(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
|
|
if (MO.isImm()) {
|
|
uint64_t Res = MO.getImm();
|
|
return (Res - 1);
|
|
}
|
|
|
|
llvm_unreachable("Unhandled expression!");
|
|
return 0;
|
|
}
|
|
|
|
uint64_t
|
|
RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert(MO.isImm() && "Slist operand must be immediate");
|
|
|
|
uint64_t Res = MO.getImm();
|
|
switch (Res) {
|
|
case 0:
|
|
return 0;
|
|
case 1:
|
|
return 1;
|
|
case 2:
|
|
return 2;
|
|
case 4:
|
|
return 3;
|
|
case 8:
|
|
return 4;
|
|
case 16:
|
|
return 5;
|
|
case 15:
|
|
return 6;
|
|
case 31:
|
|
return 7;
|
|
default:
|
|
llvm_unreachable("Unhandled Slist value!");
|
|
}
|
|
}
|
|
|
|
template <unsigned N>
|
|
unsigned
|
|
RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
|
|
if (MO.isImm()) {
|
|
uint64_t Res = MO.getImm();
|
|
assert((Res & ((1 << N) - 1)) == 0 && "LSB is non-zero");
|
|
return Res >> N;
|
|
}
|
|
|
|
return getImmOpValue(MI, OpNo, Fixups, STI);
|
|
}
|
|
|
|
uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
bool EnableRelax = STI.hasFeature(RISCV::FeatureRelax);
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
|
|
MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
|
|
unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags);
|
|
|
|
// If the destination is an immediate, there is nothing to do.
|
|
if (MO.isImm())
|
|
return MO.getImm();
|
|
|
|
assert(MO.isExpr() &&
|
|
"getImmOpValue expects only expressions or immediates");
|
|
const MCExpr *Expr = MO.getExpr();
|
|
MCExpr::ExprKind Kind = Expr->getKind();
|
|
|
|
// `RelaxCandidate` must be set to `true` in two cases:
|
|
// - The fixup's relocation gets a R_RISCV_RELAX relocation
|
|
// - The underlying instruction may be relaxed to an instruction that gets a
|
|
// `R_RISCV_RELAX` relocation.
|
|
//
|
|
// The actual emission of `R_RISCV_RELAX` will be handled in
|
|
// `RISCVAsmBackend::applyFixup`.
|
|
bool RelaxCandidate = false;
|
|
auto AsmRelaxToLinkerRelaxableWithFeature = [&](unsigned Feature) -> void {
|
|
if (!STI.hasFeature(RISCV::FeatureExactAssembly) && STI.hasFeature(Feature))
|
|
RelaxCandidate = true;
|
|
};
|
|
|
|
unsigned FixupKind = RISCV::fixup_riscv_invalid;
|
|
if (Kind == MCExpr::Specifier) {
|
|
const auto *RVExpr = cast<MCSpecifierExpr>(Expr);
|
|
FixupKind = RVExpr->getSpecifier();
|
|
switch (RVExpr->getSpecifier()) {
|
|
default:
|
|
assert(FixupKind && FixupKind < FirstTargetFixupKind &&
|
|
"invalid specifier");
|
|
break;
|
|
case ELF::R_RISCV_TPREL_ADD:
|
|
// tprel_add is only used to indicate that a relocation should be emitted
|
|
// for an add instruction used in TP-relative addressing. It should not be
|
|
// expanded as if representing an actual instruction operand and so to
|
|
// encounter it here is an error.
|
|
llvm_unreachable(
|
|
"ELF::R_RISCV_TPREL_ADD should not represent an instruction operand");
|
|
case RISCV::S_LO:
|
|
if (MIFrm == RISCVII::InstFormatI)
|
|
FixupKind = RISCV::fixup_riscv_lo12_i;
|
|
else if (MIFrm == RISCVII::InstFormatS)
|
|
FixupKind = RISCV::fixup_riscv_lo12_s;
|
|
else
|
|
llvm_unreachable("VK_LO used with unexpected instruction format");
|
|
RelaxCandidate = true;
|
|
break;
|
|
case ELF::R_RISCV_HI20:
|
|
FixupKind = RISCV::fixup_riscv_hi20;
|
|
RelaxCandidate = true;
|
|
break;
|
|
case RISCV::S_PCREL_LO:
|
|
if (MIFrm == RISCVII::InstFormatI)
|
|
FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
|
|
else if (MIFrm == RISCVII::InstFormatS)
|
|
FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
|
|
else
|
|
llvm_unreachable("VK_PCREL_LO used with unexpected instruction format");
|
|
RelaxCandidate = true;
|
|
break;
|
|
case ELF::R_RISCV_PCREL_HI20:
|
|
FixupKind = RISCV::fixup_riscv_pcrel_hi20;
|
|
RelaxCandidate = true;
|
|
break;
|
|
case RISCV::S_TPREL_LO:
|
|
if (MIFrm == RISCVII::InstFormatI)
|
|
FixupKind = ELF::R_RISCV_TPREL_LO12_I;
|
|
else if (MIFrm == RISCVII::InstFormatS)
|
|
FixupKind = ELF::R_RISCV_TPREL_LO12_S;
|
|
else
|
|
llvm_unreachable("VK_TPREL_LO used with unexpected instruction format");
|
|
RelaxCandidate = true;
|
|
break;
|
|
case ELF::R_RISCV_TPREL_HI20:
|
|
RelaxCandidate = true;
|
|
break;
|
|
case ELF::R_RISCV_CALL_PLT:
|
|
FixupKind = RISCV::fixup_riscv_call_plt;
|
|
RelaxCandidate = true;
|
|
break;
|
|
case RISCV::S_QC_ABS20:
|
|
FixupKind = RISCV::fixup_riscv_qc_abs20_u;
|
|
RelaxCandidate = true;
|
|
break;
|
|
}
|
|
} else if (Kind == MCExpr::SymbolRef || Kind == MCExpr::Binary) {
|
|
// FIXME: Sub kind binary exprs have chance of underflow.
|
|
if (MIFrm == RISCVII::InstFormatJ) {
|
|
FixupKind = RISCV::fixup_riscv_jal;
|
|
AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb);
|
|
} else if (MIFrm == RISCVII::InstFormatB) {
|
|
FixupKind = RISCV::fixup_riscv_branch;
|
|
// This might be assembler relaxed to `b<cc>; jal` but we cannot relax
|
|
// the `jal` again in the assembler.
|
|
} else if (MIFrm == RISCVII::InstFormatCJ) {
|
|
FixupKind = RISCV::fixup_riscv_rvc_jump;
|
|
AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb);
|
|
} else if (MIFrm == RISCVII::InstFormatCB) {
|
|
FixupKind = RISCV::fixup_riscv_rvc_branch;
|
|
// This might be assembler relaxed to `b<cc>; jal` but we cannot relax
|
|
// the `jal` again in the assembler.
|
|
} else if (MIFrm == RISCVII::InstFormatCI) {
|
|
FixupKind = RISCV::fixup_riscv_rvc_imm;
|
|
} else if (MIFrm == RISCVII::InstFormatI) {
|
|
FixupKind = RISCV::fixup_riscv_12_i;
|
|
} else if (MIFrm == RISCVII::InstFormatQC_EB) {
|
|
FixupKind = RISCV::fixup_riscv_qc_e_branch;
|
|
// This might be assembler relaxed to `qc.e.b<cc>; jal` but we cannot
|
|
// relax the `jal` again in the assembler.
|
|
} else if (MIFrm == RISCVII::InstFormatQC_EAI) {
|
|
FixupKind = RISCV::fixup_riscv_qc_e_32;
|
|
RelaxCandidate = true;
|
|
} else if (MIFrm == RISCVII::InstFormatQC_EJ) {
|
|
FixupKind = RISCV::fixup_riscv_qc_e_call_plt;
|
|
RelaxCandidate = true;
|
|
} else if (MIFrm == RISCVII::InstFormatNDS_BRANCH_10) {
|
|
FixupKind = RISCV::fixup_riscv_nds_branch_10;
|
|
}
|
|
}
|
|
|
|
assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
|
|
|
|
addFixup(Fixups, 0, Expr, FixupKind);
|
|
// If linker relaxation is enabled and supported by this relocation, set a bit
|
|
// so that the assembler knows the size of the instruction is not fixed/known,
|
|
// and the relocation will need a R_RISCV_RELAX relocation.
|
|
if (EnableRelax && RelaxCandidate)
|
|
Fixups.back().setLinkerRelaxable();
|
|
++MCNumFixups;
|
|
|
|
return 0;
|
|
}
|
|
|
|
unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
MCOperand MO = MI.getOperand(OpNo);
|
|
assert(MO.isReg() && "Expected a register.");
|
|
|
|
switch (MO.getReg()) {
|
|
default:
|
|
llvm_unreachable("Invalid mask register.");
|
|
case RISCV::V0:
|
|
return 0;
|
|
case RISCV::NoRegister:
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert(MO.isImm() && "Rlist operand must be immediate");
|
|
auto Imm = MO.getImm();
|
|
assert(Imm >= 4 && "EABI is currently not implemented");
|
|
return Imm;
|
|
}
|
|
unsigned
|
|
RISCVMCCodeEmitter::getRlistS0OpValue(const MCInst &MI, unsigned OpNo,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
assert(MO.isImm() && "Rlist operand must be immediate");
|
|
auto Imm = MO.getImm();
|
|
assert(Imm >= 4 && "EABI is currently not implemented");
|
|
assert(Imm != RISCVZC::RA && "Rlist operand must include s0");
|
|
return Imm;
|
|
}
|
|
|
|
#include "RISCVGenMCCodeEmitter.inc"
|