866113c2ea
A number of backends (AArch64, MIPS, ARM) have been using MCContext::reportError to report issues such as out-of-range fixup values in their TgtAsmBackend. This is great, but because MCContext couldn't easily be threaded through to the adjustFixupValue helper function from its usual callsite (applyFixup), these backends ended up adding an MCContext* argument and adding another call to applyFixup to processFixupValue. Adding an MCContext parameter to applyFixup makes this unnecessary, and even better - applyFixup can take a reference to MCContext rather than a potentially null pointer. Differential Revision: https://reviews.llvm.org/D30264 llvm-svn: 299529
92 lines
3.0 KiB
C++
92 lines
3.0 KiB
C++
//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class RISCVAsmBackend : public MCAsmBackend {
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uint8_t OSABI;
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bool Is64Bit;
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public:
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RISCVAsmBackend(uint8_t OSABI, bool Is64Bit)
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: MCAsmBackend(), OSABI(OSABI), Is64Bit(Is64Bit) {}
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~RISCVAsmBackend() override {}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value, bool IsPCRel, MCContext &Ctx) const override;
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MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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return false;
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}
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unsigned getNumFixupKinds() const override { return 1; }
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bool mayNeedRelaxation(const MCInst &Inst) const override { return false; }
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override {
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llvm_unreachable("RISCVAsmBackend::relaxInstruction() unimplemented");
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}
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
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};
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bool RISCVAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// Once support for the compressed instruction set is added, we will be able
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// to conditionally support 16-bit NOPs
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if ((Count % 4) != 0)
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return false;
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// The canonical nop on RISC-V is addi x0, x0, 0
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for (uint64_t i = 0; i < Count; i += 4)
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OW->write32(0x13);
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return true;
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}
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void RISCVAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel, MCContext &Ctx) const {
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return;
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}
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MCObjectWriter *
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RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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return createRISCVELFObjectWriter(OS, OSABI, Is64Bit);
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}
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} // end anonymous namespace
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MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options) {
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
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return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
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}
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