llvm-project/llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
Matthias Braun 538859cca3 llc: Add support for -run-pass none
This does not schedule any passes besides the ones necessary to
construct and print the machine function. This is useful to test .mir
file reading and printing.

Differential Revision: http://reviews.llvm.org/D22432

llvm-svn: 275664
2016-07-16 02:24:59 +00:00

80 lines
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# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses the stack protector stack
# object reference in the machine frame info correctly.
--- |
@.str = private unnamed_addr constant [4 x i8] c"%s\0A\00", align 1
@__stack_chk_guard = external global i8*
define i32 @test() #0 {
entry:
%StackGuardSlot = alloca i8*
%StackGuard = load i8*, i8** @__stack_chk_guard
call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot)
%test = alloca i8*, align 8
%a = alloca i8, i64 5
store i8* %a, i8** %test, align 8
%b = load i8*, i8** %test, align 8
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* %b)
call void @llvm.stackprotectorcheck(i8** @__stack_chk_guard)
ret i32 %call
}
declare i32 @printf(i8*, ...)
declare void @llvm.stackprotector(i8*, i8**) #1
declare void @llvm.stackprotectorcheck(i8**) #2
attributes #0 = { ssp "stack-protector-buffer-size"="5" }
attributes #1 = { nounwind }
attributes #2 = { nounwind argmemonly }
...
---
name: test
alignment: 4
tracksRegLiveness: true
frameInfo:
stackSize: 40
maxAlignment: 8
adjustsStack: true
hasCalls: true
# CHECK-LABEL: name: test
# CHECK: frameInfo
# CHECK: stackProtector: '%stack.0.StackGuardSlot'
stackProtector: '%stack.0.StackGuardSlot'
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
callee-saved-register: '%rbx' }
stack:
- { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 }
- { id: 1, name: test, offset: -40, size: 8, alignment: 8 }
- { id: 2, name: a, offset: -29, size: 5, alignment: 1 }
body: |
bb.0.entry:
successors: %bb.1.entry, %bb.2.entry
liveins: %rbx, %rbx
frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
%rsp = frame-setup SUB64ri8 %rsp, 32, implicit-def dead %eflags
%rbx = LOAD_STACK_GUARD :: (invariant load 8 from @__stack_chk_guard)
MOV64mr %rsp, 1, _, 24, _, %rbx
%rsi = LEA64r %rsp, 1, _, 19, _
MOV64mr %rsp, 1, _, 8, _, %rsi
%rdi = LEA64r %rip, 1, _, @.str, _
dead %eax = MOV32r0 implicit-def dead %eflags, implicit-def %al
CALL64pcrel32 @printf, csr_64, implicit %rsp, implicit %rdi, implicit %rsi, implicit %al, implicit-def %rsp, implicit-def %eax
CMP64rm killed %rbx, %rsp, 1, _, 24, _, implicit-def %eflags
JNE_1 %bb.2.entry, implicit %eflags
bb.1.entry:
liveins: %eax
%rsp = ADD64ri8 %rsp, 32, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
bb.2.entry:
CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
...