Joe Nash 7e3e9d4308

[AMDGPU] Change getLdStRegisterOperand to !cond for better diagnostic (#95475) ...

If you would hit the unexpected case in these !if trees, you'd get an
error message like "error: Not a known RegisterClass! def VReg_1..."
This can happen when changing code quite indirectly related to these
class definitions. We can use !cond here, which has a builtin facility
to throw an error if no case in the !cond statement is hit.

NFC.

2024-06-14 09:33:03 -04:00

..

AsmParser

[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)

2024-06-04 16:31:27 +01:00

Disassembler

Add clarifying parenthesis around non-trivial conditions in ternary expressions. (#90391)

2024-05-04 18:38:45 +01:00

MCA

[AMDGPU][SIInsertWaitcnts] Do not add s_waitcnt when the counters are known to be 0 already (#72830)

2023-12-15 12:33:32 +01:00

MCTargetDesc

Reland "[NFC][AMDGPU] Do not flush after printing every instruction (#95237)"

2024-06-13 08:30:06 +02:00

TargetInfo

[AMDGPU] Eliminate SIMCCodeEmitter and de-virtualise encoding methods.

2023-07-05 10:13:33 +01:00

Utils

MCExpr-ify AMDGPU PALMetadata (#93236)

2024-06-13 13:59:31 +01:00

AMDGPU.h

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04 08:10:58 +08:00

AMDGPU.td

[AMDGPU] Add a new target gfx1152 (#94534)

2024-06-06 12:16:11 -04:00

AMDGPUAliasAnalysis.cpp

[AA] Skip the layer of indirection in returning conservative results.

2023-07-28 12:13:35 -07:00

AMDGPUAliasAnalysis.h

[AA] Allow for flow-sensitive analyses.

2022-12-15 21:04:38 -08:00

AMDGPUAlwaysInlinePass.cpp

[AMDGPU] Always Inline preserved analyses (#91198)

2024-05-09 06:17:01 -04:00

AMDGPUAnnotateKernelFeatures.cpp

…

AMDGPUAnnotateUniformValues.cpp

[AMDGPU] Replace LegacyDA with Uniformity Analysis in AnnotateUniformValues

2023-02-28 13:05:38 -07:00

AMDGPUArgumentUsageInfo.cpp

[AMDGPU] Add DAG ISel support for preloaded kernel arguments

2023-09-25 09:32:59 -07:00

AMDGPUArgumentUsageInfo.h

[AMDGPU] Miscellaneous clang-format changes (#75186)

2023-12-12 14:26:04 +00:00

AMDGPUAsmPrinter.cpp

MCExpr-ify AMDGPU PALMetadata (#93236)

2024-06-13 13:59:31 +01:00

AMDGPUAsmPrinter.h

[AMDGPU] Support SIProgramInfo MCExpr for comments and remarks (#94350)

2024-06-10 12:34:06 +01:00

AMDGPUAtomicOptimizer.cpp

[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)

2024-06-10 12:14:51 +01:00

AMDGPUAttributes.def

Partially reapply "AMDGPU: Invert handling of enqueued block detection"

2023-01-12 15:02:16 -05:00

AMDGPUAttributor.cpp

[Target] Use StringRef::operator== instead of StringRef::equals (NFC) (#91072) (#91138)

2024-05-05 13:43:10 -07:00

AMDGPUCallingConv.td

Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)

2024-03-26 11:01:08 +01:00

AMDGPUCallLowering.cpp

Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)

2024-03-26 11:01:08 +01:00

AMDGPUCallLowering.h

[AMDGPU] ISel for @llvm.amdgcn.cs.chain intrinsic (#68186)

2023-11-06 12:30:07 +01:00

AMDGPUCodeGenPassBuilder.cpp

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04 08:10:58 +08:00

AMDGPUCodeGenPassBuilder.h

[NewPM][AMDGPU] Add CodeGenPassBuilder (#91040)

2024-05-19 15:57:02 +08:00

AMDGPUCodeGenPrepare.cpp

[AMDGPU] Fix missing IsExact flag when expanding vector binary operator (#86712)

2024-03-27 17:40:58 -04:00

AMDGPUCombine.td

[AMDGPU] Fix typo in function name

2024-05-06 08:55:09 +01:00

AMDGPUCombinerHelper.cpp

AMDGPU/GlobalISel: Use correct type for intrinsic ID

2024-05-30 14:31:19 +02:00

AMDGPUCombinerHelper.h

[llvm] Fix include guards

2023-06-13 10:47:18 +01:00

AMDGPUCtorDtorLowering.cpp

[llvm] Replace calls to Type::getPointerTo (NFC)

2023-11-30 13:18:51 -06:00

AMDGPUCtorDtorLowering.h

AMDGPU: Port AMDGPUCtorDtorLowering to new PM

2022-12-09 13:43:38 -05:00

AMDGPUExportClustering.cpp

…

AMDGPUExportClustering.h

…

AMDGPUFeatures.td

…

AMDGPUFrameLowering.cpp

[NFC][AMDGPU] Fix typo.

2022-08-20 08:30:42 +02:00

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

Silence illegal address computation warning (#83244)

2024-03-01 21:41:12 +05:30

AMDGPUGISel.td

[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)

2024-05-27 14:09:17 +02:00

AMDGPUGlobalISelDivergenceLowering.cpp

[CodeGen][NewPM] Split MachinePostDominators into a concrete analysis result (#95113)

2024-06-12 14:29:22 +08:00

AMDGPUGlobalISelUtils.cpp

[AMDGPU] Remove hasAtomicFaddRtnForTy as it is not used anywhere (#82841)

2024-02-23 21:14:38 -05:00

AMDGPUGlobalISelUtils.h

[AMDGPU] Remove hasAtomicFaddRtnForTy as it is not used anywhere (#82841)

2024-02-23 21:14:38 -05:00

AMDGPUHSAMetadataStreamer.cpp

MCExpr-ify SIProgramInfo (#88257)

2024-05-09 13:02:32 +01:00

AMDGPUHSAMetadataStreamer.h

[AMDGPU] Fix unittest linking error with LLVM_LINK_LLVM_DYLIB (#91727)

2024-05-11 09:18:05 +02:00

AMDGPUIGroupLP.cpp

[llvm] Use llvm::is_contained (NFC) (#95362)

2024-06-13 08:09:13 -07:00

AMDGPUIGroupLP.h

[AMDGPU] Do not attempt to fallback to default mutations (#83208)

2024-02-27 18:04:59 -08:00

AMDGPUImageIntrinsicOptimizer.cpp

[AMDGPU] Use llvm::none_of (NFC)

2024-01-24 00:27:37 -08:00

AMDGPUInsertDelayAlu.cpp

[AMDGPU] Add functions for composing and decomposing S_WAIT_DEPCTR operands

2023-07-04 11:02:12 +01:00

AMDGPUInsertSingleUseVDST.cpp

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00

AMDGPUInstCombineIntrinsic.cpp

[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)

2024-06-10 12:14:51 +01:00

AMDGPUInstrInfo.cpp

Restore "[GlobalISel] GIntrinsic subclass to represent intrinsics in Generic Machine IR"

2023-07-27 14:49:17 +05:30

AMDGPUInstrInfo.h

AMDGPU/GlobalISel: Use correct type for intrinsic ID

2024-05-30 14:31:19 +02:00

AMDGPUInstrInfo.td

[AMDGPU] Add a trap lowering workaround for gfx11 (#85854)

2024-04-24 09:43:54 -04:00

AMDGPUInstructions.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

AMDGPUInstructionSelector.cpp

AMDGPU/GlobalISel: Use correct type for intrinsic ID

2024-05-30 14:31:19 +02:00

AMDGPUInstructionSelector.h

[AMDGPU] New intrinsic llvm.amdgcn.pops.exiting.wave.id (#89612)

2024-05-22 19:47:59 +01:00

AMDGPUISelDAGToDAG.cpp

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04 08:10:58 +08:00

AMDGPUISelDAGToDAG.h

[DAG] Move isNullConstantOrUndef helper to SelectionDAGNodes.h to allow other future uses. NFC.

2024-06-12 16:32:36 +01:00

AMDGPUISelLowering.cpp

AMDGPU: Do not assert on v6x16 buffer load intrinsics (#94966)

2024-06-10 16:38:06 +02:00

AMDGPUISelLowering.h

[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)

2024-05-27 14:09:17 +02:00

AMDGPULateCodeGenPrepare.cpp

[AMDGPU] Do not widen scalar loads on GFX12 (#78724)

2024-01-19 15:30:07 +00:00

AMDGPULegalizerInfo.cpp

[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)

2024-05-27 14:09:17 +02:00

AMDGPULegalizerInfo.h

[AMDGPU] Use LSH for lowering ctlz_zero_undef.i8/i16 (#88512)

2024-05-19 21:45:24 +01:00

AMDGPULibCalls.cpp

AMDGPU: Emit 1/llvm.sqrt(x) instead of rsqrt calls in libcall handling (#92863)

2024-05-21 18:42:45 +02:00

AMDGPULibFunc.cpp

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

2023-12-11 21:01:36 -08:00

AMDGPULibFunc.h

AMDGPU: Use pown instead of pow if known integral

2023-09-01 08:22:16 -04:00

AMDGPULowerBufferFatPointers.cpp

[AMDGPULowerBufferFatPointers] Don't try to preserve flags for constant expressions

2024-06-14 12:26:29 +02:00

AMDGPULowerKernelArguments.cpp

[AMDGPU] Strengthen preload intrinsics to noundef and nonnull (#92801)

2024-06-03 16:37:08 -05:00

AMDGPULowerKernelAttributes.cpp

[AMDGPU] Add an asm directive to track code_object_version (#76267)

2024-01-21 11:54:47 -05:00

AMDGPULowerModuleLDSPass.cpp

[AMDGPU] Update removeFnAttrFromReachable to accept array of Fn Attrs. (#94188)

2024-06-06 21:20:29 +05:30

AMDGPUMachineCFGStructurizer.cpp

Use object directly instead of accessing ArrayRef (#83263)

2024-03-01 19:15:42 +05:30

AMDGPUMachineFunction.cpp

[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)

2024-01-04 19:05:12 +05:30

AMDGPUMachineFunction.h

[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)

2024-01-04 19:05:12 +05:30

AMDGPUMachineModuleInfo.cpp

…

AMDGPUMachineModuleInfo.h

std::optional::value => operator*/operator->

2022-12-17 00:42:05 +00:00

AMDGPUMacroFusion.cpp

[DAG] clang-format createBranchMacroFusionDAGMutation calls. NFC.

2023-11-20 12:13:09 +00:00

AMDGPUMacroFusion.h

…

AMDGPUMarkLastScratchLoad.cpp

[AMDGPU] Add mark last scratch load pass (#75512)

2024-01-18 09:36:44 +01:00

AMDGPUMCInstLower.cpp

[AMDGPU] Fix expensive-checks build.

2023-07-05 10:26:21 +01:00

AMDGPUMCInstLower.h

…

AMDGPUMIRFormatter.cpp

AMDGPU: Remove ImagePSV and move images to addrspace 7

2022-11-30 11:32:34 +01:00

AMDGPUMIRFormatter.h

…

AMDGPUOpenCLEnqueuedBlockLowering.cpp

[NFC] Remove Type::getInt8PtrTy (#71029)

2023-11-07 17:26:26 +01:00

AMDGPUPassRegistry.def

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04 08:10:58 +08:00

AMDGPUPerfHintAnalysis.cpp

…

AMDGPUPerfHintAnalysis.h

…

AMDGPUPostLegalizerCombiner.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

AMDGPUPredicateControl.td

[AMDGPU][TableGen][NFC] Combine predicates without using classes. (#82346)

2024-02-21 11:45:36 +00:00

AMDGPUPreLegalizerCombiner.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

AMDGPUPrintfRuntimeBinding.cpp

[NFC][RemoveDIs] Use iterators for insertion at various call-sites (#84736)

2024-03-19 16:36:29 +00:00

AMDGPUPromoteAlloca.cpp

[AMDGPU][PromoteAlloca] Don't stop when an alloca is too big to promote (#93466)

2024-05-28 08:05:50 +02:00

AMDGPUPromoteKernelArguments.cpp

[llvm] Remove uses of getWithSamePointeeType() (NFC)

2023-07-18 12:07:09 +02:00

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

AMDGPURegBankSelect.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

AMDGPURegBankSelect.h

AMDGPU/GlobalISel: Add stub custom regbankselect pass

2023-01-30 16:18:20 -04:00

AMDGPURegisterBankInfo.cpp

[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)

2024-05-27 14:09:17 +02:00

AMDGPURegisterBankInfo.h

[AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC.

2024-01-09 11:53:12 +00:00

AMDGPURegisterBanks.td

[AMDGPU][True16] Don't use the VGPR_LO/HI16 register classes. (#76440)

2023-12-28 11:48:25 +00:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (#76955)

2024-02-12 10:18:20 +01:00

AMDGPUResourceUsageAnalysis.cpp

[Target][AMDGPU] Fix TSan error on AMDGPU Target. (#79529)

2024-01-25 21:32:37 -08:00

AMDGPUResourceUsageAnalysis.h

[Target][AMDGPU] Fix TSan error on AMDGPU Target. (#79529)

2024-01-25 21:32:37 -08:00

AMDGPURewriteOutArguments.cpp

[llvm] Stop including llvm/ADT/SmallSet.h (NFC)

2023-11-11 12:32:15 -08:00

AMDGPURewriteUndefForPHI.cpp

[AMDGPU] Do not preserve UniformityInfo (#76696)

2024-01-02 13:42:56 +05:30

AMDGPUSearchableTables.td

[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)

2024-06-10 12:14:51 +01:00

AMDGPUSetWavePriority.cpp

[AMDGPU][SetWavePriority] Fix dealing with MBBInfo records.

2022-09-30 14:27:50 +01:00

AMDGPUSplitModule.cpp

[AMDGPU][SplitModule] Keep looking for more dependencies after finding an indirect call (#93480)

2024-05-28 08:18:53 +02:00

AMDGPUSplitModule.h

Reland "[AMDGPU] Add AMDGPU-specific module splitting (#89245)"

2024-05-27 10:43:00 +02:00

AMDGPUSubtarget.cpp

[AMDGPU] Swap range metadata to attribute for workitem id. (#94871)

2024-06-09 10:29:50 -04:00

AMDGPUSubtarget.h

[AMDGPU] Adding the amdgpu_num_work_groups function attribute (#79035)

2024-03-12 10:30:39 -07:00

AMDGPUTargetMachine.cpp

[NewPM][CodeGen] Port regallocfast to new pass manager (#94426)

2024-06-07 12:22:42 +08:00

AMDGPUTargetMachine.h

Reland "[AMDGPU] Add AMDGPU-specific module splitting (#89245)"

2024-05-27 10:43:00 +02:00

AMDGPUTargetObjectFile.cpp

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

2023-12-11 21:01:36 -08:00

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[AMDGPU] Vectorize more 16 bit shuffles (#90648)

2024-05-21 09:21:36 -07:00

AMDGPUTargetTransformInfo.h

[TTI] getArithmeticInstrCost - use std:nullopt to create default empty ArrayRef<const Value *> Args argument. NFC.

2024-04-24 10:51:18 +01:00

AMDGPUUnifyDivergentExitNodes.cpp

[AMDGPU] Do not preserve UniformityInfo (#76696)

2024-01-02 13:42:56 +05:30

AMDGPUUnifyDivergentExitNodes.h

[llvm] Fix include guards

2023-06-13 10:47:18 +01:00

AMDGPUUnifyMetadata.cpp

[Target] Qualify auto in range-based for loops (NFC)

2022-08-28 10:41:50 -07:00

AMDKernelCodeT.h

…

BUFInstructions.td

[AMDGPU] Change getLdStRegisterOperand to !cond for better diagnostic (#95475)

2024-06-14 09:33:03 -04:00

CaymanInstructions.td

…

CMakeLists.txt

Reland "[AMDGPU] Add AMDGPU-specific module splitting (#89245)"

2024-05-27 10:43:00 +02:00

DSDIRInstructions.td

AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537)

2024-04-03 11:35:09 -07:00

DSInstructions.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

EvergreenInstructions.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

EXPInstructions.td

[AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602)

2024-05-10 15:04:38 +01:00

FLATInstructions.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

GCNCreateVOPD.cpp

[AMDGPU] Fix implicit operands of VOPD cndmask instructions (#87788)

2024-04-16 10:14:15 +01:00

GCNDPPCombine.cpp

[AMDGPU] Support byte_sel modifier for v_cvt_f32_fp8 and v_cvt_f32_bf8 (#90887)

2024-05-02 12:03:51 -07:00

GCNHazardRecognizer.cpp

[AMDGPU] Remove some pointless fallthrough annotations

2024-05-01 16:04:35 +01:00

GCNHazardRecognizer.h

[AMDGPU][GFX11] Mitigate VALU mask write hazard

2022-10-01 16:21:24 +09:00

GCNILPSched.cpp

Add llvm::min/max_element and use it in llvm/ and mlir/ directories. (#84678)

2024-03-10 20:00:13 -07:00

GCNIterativeScheduler.cpp

[AMDGPU] Prefer lower total register usage in regions with spilling

2024-02-26 12:19:52 -08:00

GCNIterativeScheduler.h

…

GCNMinRegStrategy.cpp

[llvm] Qualify auto in range-based for loops (NFC)

2022-08-13 12:55:42 -07:00

GCNNSAReassign.cpp

[AMDGPU] Do not run GCNNSAReassign pass for GFX12 (#78185)

2024-01-17 15:22:48 +00:00

GCNPreRALongBranchReg.cpp

[AMDGPU] Reserve SGPR pair when long branches are present

2023-06-29 16:50:46 -05:00

GCNPreRAOptimizations.cpp

…

GCNProcessors.td

[AMDGPU] Add a new target gfx1152 (#94534)

2024-06-06 12:16:11 -04:00

GCNRegPressure.cpp

[AMDGPU] Prefer lower total register usage in regions with spilling

2024-02-26 12:19:52 -08:00

GCNRegPressure.h

[AMDGPU] Prefer lower total register usage in regions with spilling

2024-02-26 12:19:52 -08:00

GCNRewritePartialRegUses.cpp

[AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (#69957)

2023-11-16 16:56:46 +01:00

GCNSchedStrategy.cpp

[NFCI][AMDGPU] Try to use PressureDiff to Calculate RegPressure. (#94221)

2024-06-14 08:34:53 +02:00

GCNSchedStrategy.h

[NFCI][AMDGPU] Try to use PressureDiff to Calculate RegPressure. (#94221)

2024-06-14 08:34:53 +02:00

GCNSubtarget.h

AMDGPU: Fix creating minimum3/maximum3 nodes pre-gfx12 (#93027)

2024-05-23 15:59:43 +02:00

GCNVOPDUtils.cpp

[AMDGPU] Update VOP instructions for GFX12 (#74853)

2023-12-12 11:38:24 +01:00

GCNVOPDUtils.h

…

InstCombineTables.td

…

MIMGInstructions.td

[AMDGPU][MC] Support tfe operand in image_atomic instructions (#92469)

2024-05-29 15:55:58 -07:00

R600.h

[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)

2023-09-14 14:10:14 -07:00

R600.td

[AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (#82245)

2024-02-20 11:37:44 +00:00

R600AsmPrinter.cpp

[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2022-08-08 11:24:15 -07:00

R600AsmPrinter.h

…

R600ClauseMergePass.cpp

…

R600CodeGenPassBuilder.cpp

[NewPM][AMDGPU] Add CodeGenPassBuilder (#91040)

2024-05-19 15:57:02 +08:00

R600CodeGenPassBuilder.h

[NewPM][AMDGPU] Add CodeGenPassBuilder (#91040)

2024-05-19 15:57:02 +08:00

R600ControlFlowFinalizer.cpp

[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2022-08-08 11:24:15 -07:00

R600Defines.h

…

R600EmitClauseMarkers.cpp

…

R600ExpandSpecialInstrs.cpp

…

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

R600InstrInfo.h

…

R600InstrInfo.td

…

R600Instructions.td

[AMDGPU] Generic lowering for rint and nearbyint (#69596)

2023-11-14 18:49:21 +01:00

R600ISelDAGToDAG.cpp

Reland "[NewPM][CodeGen] Port selection dag isel to new pass manager" (#94149)

2024-06-04 08:10:58 +08:00

R600ISelLowering.cpp

[Target] Use getConstantOperandVal (NFC)

2024-01-14 00:53:29 -08:00

R600ISelLowering.h

AMDGPU: Support atomicrmw uinc_wrap/udec_wrap

2023-01-27 22:17:16 -04:00

R600MachineCFGStructurizer.cpp

[CodeGen][NewPM] Split MachinePostDominators into a concrete analysis result (#95113)

2024-06-12 14:29:22 +08:00

R600MachineFunctionInfo.cpp

CodeGen: Don't lazily construct MachineFunctionInfo

2022-12-21 10:49:32 -05:00

R600MachineFunctionInfo.h

CodeGen: Don't lazily construct MachineFunctionInfo

2022-12-21 10:49:32 -05:00

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

[NFC] Hide implementation details in anonymous namespaces

2023-01-08 17:37:02 +01:00

R600OpenCLImageTypeLoweringPass.cpp

[llvm] Use StringRef::{starts,ends}_with (NFC) (#74956)

2023-12-11 21:01:36 -08:00

R600OptimizeVectorRegisters.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

R600Packetizer.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

R600Processors.td

…

R600RegisterInfo.cpp

PEI should be able to use backward walk in replaceFrameIndicesBackward.

2022-11-18 15:57:34 +01:00

R600RegisterInfo.h

PEI should be able to use backward walk in replaceFrameIndicesBackward.

2022-11-18 15:57:34 +01:00

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

AMDGPU: Clean up LDS-related occupancy calculations

2023-01-23 21:43:06 +01:00

R600Subtarget.h

…

R600TargetMachine.cpp

[NewPM][AMDGPU] Add CodeGenPassBuilder (#91040)

2024-05-19 15:57:02 +08:00

R600TargetMachine.h

[NewPM][AMDGPU] Add CodeGenPassBuilder (#91040)

2024-05-19 15:57:02 +08:00

R600TargetTransformInfo.cpp

[llvm][TypeSize] Fix addition/subtraction in TypeSize. (#72979)

2023-11-22 08:52:53 +00:00

R600TargetTransformInfo.h

[LV][NFC] Use ElementCount for getMaxInterleaveFactor

2023-02-22 10:15:05 +00:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

[AMDGPU] Fix incorrect stepping in gdb for amdgcn.end.cf intrinsic. (#83010)

2024-05-02 12:59:31 +02:00

SIDefines.h

MCExpr-ify amd_kernel_code_t (#91587)

2024-05-22 13:45:45 +01:00

SIFixSGPRCopies.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

SIFixVGPRCopies.cpp

AMDGPU: Make SIFixVGPRCopies preserve everything

2023-07-06 10:26:21 -04:00

SIFoldOperands.cpp

[AMDGPU] Don't optimize agpr phis if the operand doesn't have subreg use (#91267)

2024-05-07 16:44:00 -04:00

SIFormMemoryClauses.cpp

[AMDGPU] Make use of MachineInstr::all_defs and all_uses. NFCI.

2023-06-05 10:32:33 +01:00

SIFrameLowering.cpp

[AMDGPU] Reserved private memory register during PEI (#93536)

2024-05-29 15:10:44 +05:30

SIFrameLowering.h

Revert "[AMDGPU] Compiler should synthesize private buffer resource descriptor from flat_scratch_init" (#81234)

2024-02-09 09:57:38 +01:00

SIInsertHardClauses.cpp

[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)

2024-03-06 17:40:13 +00:00

SIInsertWaitcnts.cpp

[CodeGen][NewPM] Split MachinePostDominators into a concrete analysis result (#95113)

2024-06-12 14:29:22 +08:00

SIInstrFormats.td

[AMDGPU][NFC] Eliminate GCNPredicateControl. (#93964)

2024-05-31 16:28:43 +01:00

SIInstrInfo.cpp

[AMDGPU] Remove SIWholeQuadMode pseudo wavemode optimization (#94133)

2024-06-12 15:51:40 +09:00

SIInstrInfo.h

[AMDGPU] Enhance s_waitcnt insertion before barrier for gfx12 (#90595)

2024-05-01 11:37:13 +01:00

SIInstrInfo.td

[AMDGPU] Change getLdStRegisterOperand to !cond for better diagnostic (#95475)

2024-06-14 09:33:03 -04:00

SIInstructions.td

[AMDGPU] Extend llvm.amdgcn.set.inactive intrinsic to support Reg32/Reg64 types (#94457)

2024-06-14 14:15:28 +02:00

SIISelLowering.cpp

AMDGPU: Fix buffer intrinsic store of bfloat (#95377)

2024-06-13 13:13:04 +02:00

SIISelLowering.h

[RFC][AMDGPU] Remove old llvm.amdgcn.buffer.* and tbuffer intrinsics (#93801)

2024-06-10 12:14:51 +01:00

SILateBranchLowering.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

SILoadStoreOptimizer.cpp

[AMDGPU] Promote immediate offset to atomics (#94043)

2024-06-06 12:05:51 -07:00

SILowerControlFlow.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

SILowerI1Copies.cpp

[CodeGen][NewPM] Split MachinePostDominators into a concrete analysis result (#95113)

2024-06-12 14:29:22 +08:00

SILowerI1Copies.h

AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)

2024-02-05 14:07:01 +01:00

SILowerSGPRSpills.cpp

[AMDGPU] Fix end() iterator dereference in SILowerSGPRSpills (#88828)

2024-04-18 09:34:27 -05:00

SILowerWWMCopies.cpp

Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"

2023-07-31 20:15:45 -04:00

SIMachineFunctionInfo.cpp

[AMDGPU] Fix typo in #89773

2024-04-29 11:57:06 +01:00

SIMachineFunctionInfo.h

Use llvm::less_first (NFC) (#94136)

2024-06-02 07:45:50 -07:00

SIMachineScheduler.cpp

Add llvm::min/max_element and use it in llvm/ and mlir/ directories. (#84678)

2024-03-10 20:00:13 -07:00

SIMachineScheduler.h

…

SIMemoryLegalizer.cpp

[AMDGPU] Add amdgpu-as MMRA for fences (#78572)

2024-05-27 12:17:04 +02:00

SIModeRegister.cpp

[AMDGPU] Fix mode register pass for constrained FP operations (#90085)

2024-05-03 19:47:15 +02:00

SIModeRegisterDefaults.cpp

Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)

2024-05-06 09:09:19 +02:00

SIModeRegisterDefaults.h

Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)

2024-05-06 09:09:19 +02:00

SIOptimizeExecMasking.cpp

Reapply "Convert many LivePhysRegs uses to LiveRegUnits" (#84338)

2024-03-08 19:05:00 +05:30

SIOptimizeExecMaskingPreRA.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

SIOptimizeVGPRLiveRange.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

SIPeepholeSDWA.cpp

[AMDGPU] Don't form sext/abs/neg fp8 cvt (#83843)

2024-03-06 10:38:20 +01:00

SIPostRABundler.cpp

[MC] Add MCRegisterInfo::regunits for iteration over register units

2023-06-16 05:39:50 +03:00

SIPreAllocateWWMRegs.cpp

[AMDGPU] Remove SIWholeQuadMode pseudo wavemode optimization (#94133)

2024-06-12 15:51:40 +09:00

SIPreEmitPeephole.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

SIProgramInfo.cpp

MCExpr-ify SIProgramInfo (#88257)

2024-05-09 13:02:32 +01:00

SIProgramInfo.h

[AMDGPU] Fix unittest linking error with LLVM_LINK_LLVM_DYLIB (#91727)

2024-05-11 09:18:05 +02:00

SIRegisterInfo.cpp

[CodeGen][NewPM] Split MachineDominatorTree into a concrete analysis result (#94571)

2024-06-11 21:27:14 +08:00

SIRegisterInfo.h

[CodeGen] Make some includes explicit (NFC)

2023-11-24 14:43:18 +01:00

SIRegisterInfo.td

[AMDGPU] Extend llvm.amdgcn.set.inactive intrinsic to support Reg32/Reg64 types (#94457)

2024-06-14 14:15:28 +02:00

SISchedule.td

AMDGPU: Correct cycle counts for f64 mfma on gfx940 (#83782)

2024-03-06 09:36:01 +05:30

SIShrinkInstructions.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

SIWholeQuadMode.cpp

[AMDGPU] Remove SIWholeQuadMode pseudo wavemode optimization (#94133)

2024-06-12 15:51:40 +09:00

SMInstructions.td

[AMDGPU] Do not override PseudoInstr in SMEM Pseudo definitions. NFC.

2024-06-04 17:30:10 +01:00

SOPInstructions.td

[AMDGPU] Copy Defs and Uses from Pseudo to Real Instructions (#93004)

2024-05-31 08:40:54 +02:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU][NFC] Rename the clamp modifier definition to follow the prevailing convention. (#94353)

2024-06-04 16:31:27 +01:00

VOP1Instructions.td

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00

VOP2Instructions.td

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00

VOP3Instructions.td

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00

VOP3PInstructions.td

Add mad support for v_pk_* 16 bit integer (#95104)

2024-06-13 16:46:40 +01:00

VOPCInstructions.td

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00

VOPDInstructions.td

[AMDGPU] Update VOP instructions for GFX12 (#74853)

2023-12-12 11:38:24 +01:00

VOPInstructions.td

[AMDGPU] Exclude certain opcodes from being marked as single use (#91802)

2024-06-12 10:43:23 +01:00