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llvm-project/llvm/lib/Target/RISCV
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Brandon Wu 23c0850d2e
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914) 
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/56
Resolved https://github.com/llvm/llvm-project/issues/106700.
This enables inline asm to have vcix_state to be a clobbered register
thus disable reordering between VCIX intrinsics and inline asm.
2024-09-30 23:52:35 -07:00
..
AsmParser
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
Disassembler
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
GISel
Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"
2024-09-20 07:01:17 -07:00
MCA
[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc
2024-04-24 09:29:20 -07:00
MCTargetDesc
[RISCV] Don't delete all fixups in RISCVMCCodeEmitter::expandLongCondBr. (#109513)
2024-09-22 22:31:36 -07:00
TargetInfo
…
CMakeLists.txt
Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"
2024-09-20 07:01:17 -07:00
RISCV.h
Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"
2024-09-20 07:01:17 -07:00
RISCV.td
[RISCV] Add scheduling model for Syntacore SCR7 (#108814)
2024-09-17 18:52:55 +03:00
RISCVAsmPrinter.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVCallingConv.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVCallingConv.h
[RISCV] Reduce the interface to RISCVCCAssignFn. NFC (#107503)
2024-09-06 09:28:33 -07:00
RISCVCallingConv.td
[RISCV] RISCV vector calling convention (1/2) (#77560)
2024-03-27 23:03:13 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)
2024-08-01 09:37:42 +08:00
RISCVCombine.td
Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"
2024-09-20 07:01:17 -07:00
RISCVConstantPoolValue.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVConstantPoolValue.h
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVFeatures.td
[RISCV] Mark Zacas as non-experimental (#109651)
2024-09-25 06:14:43 +01:00
RISCVFrameLowering.cpp
[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)
2024-09-30 11:44:23 -07:00
RISCVFrameLowering.h
[RISCV] Add CFI information for vector callee-saved registers (#86811)
2024-04-17 10:42:40 +08:00
RISCVGatherScatterLowering.cpp
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
RISCVGISel.td
[RISCV][GISel] Remove unused isel patterns for s32 shifts with s64 shift amount.
2024-09-30 23:18:06 -07:00
RISCVIndirectBranchTracking.cpp
[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)
2024-08-08 13:22:59 +08:00
RISCVInsertReadWriteCSR.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInsertVSETVLI.cpp
[RISCV] Rename merge operand -> passthru. NFC (#100330)
2024-07-30 17:47:00 +08:00
RISCVInsertWriteVXRM.cpp
[CodeGen] Make the parameter TRI required in some functions. (#85968)
2024-04-24 14:24:14 +01:00
RISCVInstrFormats.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types
2024-04-03 15:27:15 -07:00
RISCVInstrInfo.cpp
[RISCV] Fold vfmv.f.s of f16 into load from stack (#110214)
2024-10-01 14:09:56 +08:00
RISCVInstrInfo.h
[CodeGen] Add generic INIT_UNDEF pseudo (#106744)
2024-09-05 09:34:39 +02:00
RISCVInstrInfo.td
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVInstrInfoA.td
[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)
2024-08-12 09:34:02 -07:00
RISCVInstrInfoC.td
[RISCV] Fix InsnCI register type (#100113)
2024-07-23 21:19:57 +08:00
RISCVInstrInfoD.td
[RISCV] Fix fneg.d/fabs.d aliasing handling for Zdinx. Add missing fmv.s/d aliases.
2024-09-10 11:44:04 -07:00
RISCVInstrInfoF.td
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
RISCVInstrInfoM.td
[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)
2024-08-12 09:34:02 -07:00
RISCVInstrInfoSFB.td
…
RISCVInstrInfoV.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoVPseudos.td
[NFC] Fix typos in comments (#109765)
2024-09-24 11:19:56 +02:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add explicit XLenVT cast to vector load/store patterns.
2024-09-23 16:02:58 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284)
2024-09-11 21:13:26 -07:00
RISCVInstrInfoXCV.td
[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)
2024-10-01 11:22:02 +10:00
RISCVInstrInfoXSf.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)
2024-08-30 07:46:06 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
RISCVInstrInfoXwch.td
[RISCV] Add QingKe "XW" compressed opcode extension (#97925)
2024-07-11 11:10:02 +08:00
RISCVInstrInfoZa.td
DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)
2024-06-13 11:52:22 +02:00
RISCVInstrInfoZalasr.td
…
RISCVInstrInfoZb.td
[RISCV] Improve BCLRITwoBitsMaskHigh SDNodeXForm. NFC
2024-08-19 10:32:47 -07:00
RISCVInstrInfoZc.td
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVInstrInfoZcmop.td
[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)
2024-04-15 22:33:14 -07:00
RISCVInstrInfoZfa.td
[RISCV] Expand Zfa fli+fneg cases during lowering instead of during isel. (#108316)
2024-09-11 22:31:45 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Remove RISCVISD::FP_ROUND_BF16.
2024-09-03 20:18:01 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZimop.td
[RISCV] Zimop/Zcmop are ratified
2024-04-08 16:40:02 +08:00
RISCVInstrInfoZk.td
…
RISCVInstrInfoZvfbf.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVInstrInfoZvk.td
[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)
2024-09-05 15:27:48 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVISelDAGToDAG.h
[RISCV] Generalize RISCVDAGToDAGISel::selectFPImm to handle bitcasts from int to FP. (#108284)
2024-09-11 21:13:26 -07:00
RISCVISelLowering.cpp
[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)
2024-09-27 13:48:01 -07:00
RISCVISelLowering.h
[RISCV] Software guard direct calls in large code model (#109377)
2024-09-27 13:04:16 +08:00
RISCVLandingPadSetup.cpp
[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)
2024-08-08 13:22:59 +08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[llvm-project] Fix typo "seperate" (#95373)
2024-06-13 20:20:27 +01:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC
2024-06-27 18:42:27 -07:00
RISCVProcessors.td
[RISCV] Add scheduling model for Syntacore SCR7 (#108814)
2024-09-17 18:52:55 +03:00
RISCVProfiles.td
[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356)
2024-08-08 09:15:43 -07:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
RISCVRegisterInfo.cpp
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
RISCVRegisterInfo.h
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
RISCVRegisterInfo.td
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
RISCVSchedRocket.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedSiFive7.td
[RISCV][SiFive7] Change Latency of VCIX to the default (#106497)
2024-09-05 13:01:29 -04:00
RISCVSchedSiFiveP400.td
[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)
2024-08-19 09:41:42 -04:00
RISCVSchedSiFiveP600.td
[RISCV] Rename merge operand -> passthru. NFC (#100330)
2024-07-30 17:47:00 +08:00
RISCVSchedSyntacoreSCR1.td
[RISCV][NFC] Cleanup SCR1 sched model (#96088)
2024-06-20 18:14:09 +03:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Add scheduling model for Syntacore SCR7 (#108814)
2024-09-17 18:52:55 +03:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)
2024-08-14 11:42:31 +03:00
RISCVSchedule.td
[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948)
2024-06-19 12:37:47 +03:00
RISCVScheduleV.td
[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671)
2024-09-01 21:02:06 -07:00
RISCVScheduleXSf.td
[RISCV] Add scheduling information for SiFive VCIX (#86093)
2024-04-16 13:55:45 +08:00
RISCVScheduleZb.td
[RISCV] Add sched classes for Zbb integer min max instructions
2024-03-14 06:02:42 -07:00
RISCVScheduleZvk.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSchedXiangShanNanHu.td
[RISCV] Add Sched classes for vector crypto instructions (#90068)
2024-05-03 11:11:29 -04:00
RISCVSubtarget.cpp
[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)
2024-08-08 09:17:43 -07:00
RISCVSubtarget.h
[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)
2024-09-16 09:48:25 +02:00
RISCVSystemOperands.td
[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)
2024-08-21 19:23:07 -07:00
RISCVTargetMachine.cpp
Revert "[RISCV][GISEL] Introduce the RISCVPostLegalizerLowering pass (#108991)"
2024-09-20 07:01:17 -07:00
RISCVTargetMachine.h
[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)
2024-07-02 18:48:28 -07:00
RISCVTargetObjectFile.cpp
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
RISCVTargetObjectFile.h
[Driver] Default -msmall-data-limit= to 0 and clean up code
2024-08-19 18:20:02 -07:00
RISCVTargetTransformInfo.cpp
[RISCV][TTI] Adjust constant materialization cost for (z/s)ext from i1 (#110282)
2024-09-27 10:53:45 -07:00
RISCVTargetTransformInfo.h
[TTI][RISCV] Model cost of loading constants arms of selects and compares (#109824)
2024-09-25 07:25:57 -07:00
RISCVVectorPeephole.cpp
[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)
2024-09-10 18:47:20 -07:00
RISCVZacasABIFix.cpp
[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)
2024-09-19 13:39:56 +01:00