2a6c871596
For a long time, the InstCombine pass handled target specific intrinsics. Having target specific code in general passes was noted as an area for improvement for a long time. D81728 moves most target specific code out of the InstCombine pass. Applying the target specific combinations in an extra pass would probably result in inferior optimizations compared to the current fixed-point iteration, therefore the InstCombine pass resorts to newly introduced functions in the TargetTransformInfo when it encounters unknown intrinsics. The patch should not have any effect on generated code (under the assumption that code never uses intrinsics from a foreign target). This introduces three new functions: TargetTransformInfo::instCombineIntrinsic TargetTransformInfo::simplifyDemandedUseBitsIntrinsic TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic A few target specific parts are left in the InstCombine folder, where it makes sense to share code. The largest left-over part in InstCombineCalls.cpp is the code shared between arm and aarch64. This allows to move about 3000 lines out from InstCombine to the targets. Differential Revision: https://reviews.llvm.org/D81728
303 lines
12 KiB
C++
303 lines
12 KiB
C++
//===- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AMDGPU target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDGPUTargetMachine.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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namespace llvm {
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class AMDGPUTargetLowering;
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class InstCombiner;
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class Loop;
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class ScalarEvolution;
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class Type;
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class Value;
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class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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using BaseT = BasicTTIImplBase<AMDGPUTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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Triple TargetTriple;
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const GCNSubtarget *ST;
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const TargetLoweringBase *TLI;
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const TargetSubtargetInfo *getST() const { return ST; }
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const TargetLoweringBase *getTLI() const { return TLI; }
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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TargetTriple(TM->getTargetTriple()),
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ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
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TLI(ST->getTargetLowering()) {}
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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};
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class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
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using BaseT = BasicTTIImplBase<GCNTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const GCNSubtarget *ST;
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const SITargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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bool IsGraphicsShader;
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bool HasFP32Denormals;
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unsigned MaxVGPRs;
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const FeatureBitset InlineFeatureIgnoreList = {
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// Codegen control options which don't matter.
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AMDGPU::FeatureEnableLoadStoreOpt,
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AMDGPU::FeatureEnableSIScheduler,
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AMDGPU::FeatureEnableUnsafeDSOffsetFolding,
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AMDGPU::FeatureFlatForGlobal,
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AMDGPU::FeaturePromoteAlloca,
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AMDGPU::FeatureUnalignedBufferAccess,
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AMDGPU::FeatureUnalignedScratchAccess,
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AMDGPU::FeatureAutoWaitcntBeforeBarrier,
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// Property of the kernel/environment which can't actually differ.
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AMDGPU::FeatureSGPRInitBug,
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AMDGPU::FeatureXNACK,
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AMDGPU::FeatureTrapHandler,
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AMDGPU::FeatureCodeObjectV3,
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// The default assumption needs to be ecc is enabled, but no directly
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// exposed operations depend on it, so it can be safely inlined.
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AMDGPU::FeatureSRAMECC,
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// Perf-tuning features
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AMDGPU::FeatureFastFMAF32,
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AMDGPU::HalfRate64Ops
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};
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const GCNSubtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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static inline int getFullRateInstrCost() {
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return TargetTransformInfo::TCC_Basic;
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}
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static inline int getHalfRateInstrCost() {
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return 2 * TargetTransformInfo::TCC_Basic;
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}
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// TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
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// should be 2 or 4.
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static inline int getQuarterRateInstrCost() {
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return 3 * TargetTransformInfo::TCC_Basic;
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}
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// On some parts, normal fp64 operations are half rate, and others
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// quarter. This also applies to some integer operations.
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inline int get64BitInstrCost() const {
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return ST->hasHalfRate64Ops() ?
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getHalfRateInstrCost() : getQuarterRateInstrCost();
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}
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public:
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explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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ST(static_cast<const GCNSubtarget*>(TM->getSubtargetImpl(F))),
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TLI(ST->getTargetLowering()),
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CommonTTI(TM, F),
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IsGraphicsShader(AMDGPU::isShader(F.getCallingConv())),
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HasFP32Denormals(AMDGPU::SIModeRegisterDefaults(F).allFP32Denormals()),
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MaxVGPRs(ST->getMaxNumVGPRs(
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std::max(ST->getWavesPerEU(F).first,
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ST->getWavesPerEUForWorkGroup(
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ST->getFlatWorkGroupSizes(F).second)))) {}
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bool hasBranchDivergence() { return true; }
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bool useGPUDivergenceAnalysis() const;
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TTI::PSK_FastHardware;
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}
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unsigned getHardwareNumberOfRegisters(bool Vector) const;
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unsigned getNumberOfRegisters(bool Vector) const;
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unsigned getNumberOfRegisters(unsigned RCID) const;
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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Type *getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
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unsigned SrcAddrSpace, unsigned DestAddrSpace,
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unsigned SrcAlign, unsigned DestAlign) const;
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void getMemcpyLoopResidualLoweringType(SmallVectorImpl<Type *> &OpsOut,
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LLVMContext &Context,
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unsigned RemainingBytes,
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unsigned SrcAddrSpace,
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unsigned DestAddrSpace,
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unsigned SrcAlign,
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unsigned DestAlign) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind);
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bool isInlineAsmSourceOfDivergence(const CallInst *CI,
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ArrayRef<unsigned> Indices = {}) const;
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int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
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bool isSourceOfDivergence(const Value *V) const;
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bool isAlwaysUniform(const Value *V) const;
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unsigned getFlatAddressSpace() const {
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// Don't bother running InferAddressSpaces pass on graphics shaders which
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// don't use flat addressing.
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if (IsGraphicsShader)
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return -1;
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return AMDGPUAS::FLAT_ADDRESS;
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}
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bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
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Intrinsic::ID IID) const;
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Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
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Value *NewV) const;
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Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const;
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Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const;
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unsigned getVectorSplitCost() { return 0; }
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unsigned getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index,
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VectorType *SubTp);
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bool areInlineCompatible(const Function *Caller,
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const Function *Callee) const;
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unsigned getInliningThresholdMultiplier() { return 11; }
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int getInlinerVectorBonusPercent() { return 0; }
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int getArithmeticReductionCost(
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unsigned Opcode,
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VectorType *Ty,
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bool IsPairwise,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
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int getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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int getMinMaxReductionCost(
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VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput);
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};
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class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
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using BaseT = BasicTTIImplBase<R600TTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const R600Subtarget *ST;
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const AMDGPUTargetLowering *TLI;
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AMDGPUTTIImpl CommonTTI;
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public:
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explicit R600TTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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ST(static_cast<const R600Subtarget*>(TM->getSubtargetImpl(F))),
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TLI(ST->getTargetLowering()),
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CommonTTI(TM, F) {}
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const R600Subtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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unsigned getHardwareNumberOfRegisters(bool Vec) const;
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unsigned getNumberOfRegisters(bool Vec) const;
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
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unsigned AddrSpace) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind);
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int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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