fc3b7874b6
For more details about this instruction, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: RKSimon, skan Differential Revision: https://reviews.llvm.org/D155146
23 lines
1.0 KiB
C
23 lines
1.0 KiB
C
// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sha512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sha512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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#include <immintrin.h>
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__m256i test_mm256_sha512msg1_epi64(__m256i __A, __m128i __B) {
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// CHECK-LABEL: @test_mm256_sha512msg1_epi64(
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// CHECK: call <4 x i64> @llvm.x86.vsha512msg1(<4 x i64> %{{.*}}, <2 x i64> %{{.*}})
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return _mm256_sha512msg1_epi64(__A, __B);
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}
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__m256i test_mm256_sha512msg2_epi64(__m256i __A, __m256i __B) {
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// CHECK-LABEL: @test_mm256_sha512msg2_epi64(
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// CHECK: call <4 x i64> @llvm.x86.vsha512msg2(<4 x i64> %{{.*}}, <4 x i64> %{{.*}})
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return _mm256_sha512msg2_epi64(__A, __B);
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}
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__m256i test_mm256_sha512rnds2_epi64(__m256i __A, __m256i __B, __m128i __C) {
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// CHECK-LABEL: @test_mm256_sha512rnds2_epi64(
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// CHECK: call <4 x i64> @llvm.x86.vsha512rnds2(<4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <2 x i64> %{{.*}})
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return _mm256_sha512rnds2_epi64(__A, __B, __C);
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}
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