8624075105
The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.
248 lines
6.6 KiB
LLVM
248 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; These test how the immediate in an addition is materialized.
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define i32 @add_positive_low_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_low_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_low_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addiw a0, a0, 2047
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2047
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ret i32 %1
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}
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define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_low_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_low_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addiw a0, a0, 1
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2048
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ret i32 %1
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}
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define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_high_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_high_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addiw a0, a0, 2047
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; RV64I-NEXT: ret
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%1 = add i32 %a, 4094
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ret i32 %1
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}
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define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_positive_high_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_positive_high_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1
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; RV64I-NEXT: addi a1, a1, -1
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, 4095
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ret i32 %1
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}
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define i32 @add_negative_high_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_high_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_high_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addiw a0, a0, -2048
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; RV64I-NEXT: ret
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%1 = add i32 %a, -2048
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ret i32 %1
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}
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define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_high_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_high_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: addiw a0, a0, -1
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; RV64I-NEXT: ret
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%1 = add i32 %a, -2049
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ret i32 %1
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}
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define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_low_bound_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: addi a0, a0, -2048
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_low_bound_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -2048
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; RV64I-NEXT: addiw a0, a0, -2048
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; RV64I-NEXT: ret
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%1 = add i32 %a, -4096
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ret i32 %1
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}
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define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
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; RV32I-LABEL: add_negative_low_bound_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a1, 1048575
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; RV32I-NEXT: addi a1, a1, -1
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_negative_low_bound_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a1, 1048575
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; RV64I-NEXT: addi a1, a1, -1
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; RV64I-NEXT: addw a0, a0, a1
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; RV64I-NEXT: ret
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%1 = add i32 %a, -4097
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ret i32 %1
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}
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define i32 @add32_accept(i32 %a) nounwind {
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; RV32I-LABEL: add32_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 952
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addiw a0, a0, 952
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2999
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ret i32 %1
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}
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define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
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; RV32I-LABEL: add32_sext_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 952
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_sext_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addiw a0, a0, 952
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; RV64I-NEXT: ret
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%1 = add i32 %a, 2999
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ret i32 %1
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}
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@gv0 = global i32 0, align 4
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define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {
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; RV32I-LABEL: add32_sext_reject_on_rv64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 2047
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; RV32I-NEXT: addi a0, a0, 953
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; RV32I-NEXT: lui a1, %hi(gv0)
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; RV32I-NEXT: sw a0, %lo(gv0)(a1)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_sext_reject_on_rv64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addiw a0, a0, 953
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; RV64I-NEXT: lui a1, %hi(gv0)
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; RV64I-NEXT: sw a0, %lo(gv0)(a1)
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; RV64I-NEXT: ret
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%b = add nsw i32 %a, 3000
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store i32 %b, ptr @gv0, align 4
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ret i32 %b
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}
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define i64 @add64_accept(i64 %a) nounwind {
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; RV32I-LABEL: add64_accept:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, a0, 2047
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; RV32I-NEXT: addi a2, a2, 952
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; RV32I-NEXT: sltu a0, a2, a0
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; RV32I-NEXT: add a1, a1, a0
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add64_accept:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, 2047
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; RV64I-NEXT: addi a0, a0, 952
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; RV64I-NEXT: ret
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%1 = add i64 %a, 2999
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ret i64 %1
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}
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@ga = global i32 0, align 4
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@gb = global i32 0, align 4
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define void @add32_reject() nounwind {
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; RV32I-LABEL: add32_reject:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a0, %hi(ga)
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; RV32I-NEXT: lw a1, %lo(ga)(a0)
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; RV32I-NEXT: lui a2, %hi(gb)
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; RV32I-NEXT: lw a3, %lo(gb)(a2)
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; RV32I-NEXT: lui a4, 1
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; RV32I-NEXT: addi a4, a4, -1096
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; RV32I-NEXT: add a1, a1, a4
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; RV32I-NEXT: add a3, a3, a4
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; RV32I-NEXT: sw a1, %lo(ga)(a0)
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; RV32I-NEXT: sw a3, %lo(gb)(a2)
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add32_reject:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, %hi(ga)
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; RV64I-NEXT: lw a1, %lo(ga)(a0)
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; RV64I-NEXT: lui a2, %hi(gb)
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; RV64I-NEXT: lw a3, %lo(gb)(a2)
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; RV64I-NEXT: lui a4, 1
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; RV64I-NEXT: addi a4, a4, -1096
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; RV64I-NEXT: add a1, a1, a4
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; RV64I-NEXT: add a3, a3, a4
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; RV64I-NEXT: sw a1, %lo(ga)(a0)
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; RV64I-NEXT: sw a3, %lo(gb)(a2)
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; RV64I-NEXT: ret
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%1 = load i32, ptr @ga, align 4
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%2 = load i32, ptr @gb, align 4
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%3 = add i32 %1, 3000
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%4 = add i32 %2, 3000
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store i32 %3, ptr @ga, align 4
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store i32 %4, ptr @gb, align 4
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ret void
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}
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