3ac9fe69f7
This commit includes the necessary changes to clang and LLVM to support codegen of `RVE` and the `ilp32e`/`lp64e` ABIs. The differences between `RVE` and `RVI` are: * `RVE` reduces the integer register count to 16(x0-x16). * The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits. `RVE` can be combined with all current standard extensions. The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are: * Only 6 integer argument registers (rather than 8). * Only 2 callee-saved registers (rather than 12). * A Stack Alignment of 32bits (rather than 128bits). * ilp32e isn't compatible with D ISA extension. If `ilp32e` or `lp64` is used with an ISA that has any of the registers x16-x31 and f0-f31, then these registers are considered temporaries. To be compatible with the implementation of ilp32e in GCC, we don't use aligned registers to pass variadic arguments and set stack alignment\ to 4-bytes for types with length of 2*XLEN. FastCC is also supported on RVE, while GHC isn't since there is only one avaiable register. Differential Revision: https://reviews.llvm.org/D70401
130 lines
4.9 KiB
LLVM
130 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -target-abi ilp32e -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-ILP32E
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -target-abi lp64e -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I-LP64E
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declare void @callee(ptr, ptr)
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define void @caller(i32 %n) {
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; RV32I-LABEL: caller:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -64
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; RV32I-NEXT: .cfi_def_cfa_offset 64
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; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
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; RV32I-NEXT: .cfi_offset ra, -4
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; RV32I-NEXT: .cfi_offset s0, -8
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; RV32I-NEXT: .cfi_offset s1, -12
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; RV32I-NEXT: addi s0, sp, 64
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; RV32I-NEXT: .cfi_def_cfa s0, 0
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; RV32I-NEXT: andi sp, sp, -64
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; RV32I-NEXT: mv s1, sp
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; RV32I-NEXT: addi a0, a0, 15
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; RV32I-NEXT: andi a0, a0, -16
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; RV32I-NEXT: sub a0, sp, a0
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; RV32I-NEXT: mv sp, a0
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; RV32I-NEXT: mv a1, s1
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; RV32I-NEXT: call callee
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; RV32I-NEXT: addi sp, s0, -64
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; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, 64
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; RV32I-NEXT: ret
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;
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; RV32I-ILP32E-LABEL: caller:
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; RV32I-ILP32E: # %bb.0:
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; RV32I-ILP32E-NEXT: addi sp, sp, -64
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; RV32I-ILP32E-NEXT: .cfi_def_cfa_offset 64
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; RV32I-ILP32E-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
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; RV32I-ILP32E-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
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; RV32I-ILP32E-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
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; RV32I-ILP32E-NEXT: .cfi_offset ra, -4
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; RV32I-ILP32E-NEXT: .cfi_offset s0, -8
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; RV32I-ILP32E-NEXT: .cfi_offset s1, -12
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; RV32I-ILP32E-NEXT: addi s0, sp, 64
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; RV32I-ILP32E-NEXT: .cfi_def_cfa s0, 0
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; RV32I-ILP32E-NEXT: andi sp, sp, -64
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; RV32I-ILP32E-NEXT: mv s1, sp
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; RV32I-ILP32E-NEXT: addi a0, a0, 3
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; RV32I-ILP32E-NEXT: andi a0, a0, -4
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; RV32I-ILP32E-NEXT: sub a0, sp, a0
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; RV32I-ILP32E-NEXT: mv sp, a0
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; RV32I-ILP32E-NEXT: mv a1, s1
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; RV32I-ILP32E-NEXT: call callee
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; RV32I-ILP32E-NEXT: addi sp, s0, -64
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; RV32I-ILP32E-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
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; RV32I-ILP32E-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
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; RV32I-ILP32E-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
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; RV32I-ILP32E-NEXT: addi sp, sp, 64
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; RV32I-ILP32E-NEXT: ret
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;
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; RV64I-LABEL: caller:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -64
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; RV64I-NEXT: .cfi_def_cfa_offset 64
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; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
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; RV64I-NEXT: .cfi_offset ra, -8
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; RV64I-NEXT: .cfi_offset s0, -16
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; RV64I-NEXT: .cfi_offset s1, -24
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; RV64I-NEXT: addi s0, sp, 64
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; RV64I-NEXT: .cfi_def_cfa s0, 0
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; RV64I-NEXT: andi sp, sp, -64
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; RV64I-NEXT: mv s1, sp
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: addi a0, a0, 15
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; RV64I-NEXT: andi a0, a0, -16
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; RV64I-NEXT: sub a0, sp, a0
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; RV64I-NEXT: mv sp, a0
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; RV64I-NEXT: mv a1, s1
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; RV64I-NEXT: call callee
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; RV64I-NEXT: addi sp, s0, -64
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; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
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; RV64I-NEXT: addi sp, sp, 64
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; RV64I-NEXT: ret
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;
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; RV64I-LP64E-LABEL: caller:
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; RV64I-LP64E: # %bb.0:
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; RV64I-LP64E-NEXT: addi sp, sp, -64
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; RV64I-LP64E-NEXT: .cfi_def_cfa_offset 64
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; RV64I-LP64E-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
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; RV64I-LP64E-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
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; RV64I-LP64E-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
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; RV64I-LP64E-NEXT: .cfi_offset ra, -8
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; RV64I-LP64E-NEXT: .cfi_offset s0, -16
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; RV64I-LP64E-NEXT: .cfi_offset s1, -24
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; RV64I-LP64E-NEXT: addi s0, sp, 64
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; RV64I-LP64E-NEXT: .cfi_def_cfa s0, 0
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; RV64I-LP64E-NEXT: andi sp, sp, -64
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; RV64I-LP64E-NEXT: mv s1, sp
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; RV64I-LP64E-NEXT: slli a0, a0, 32
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; RV64I-LP64E-NEXT: srli a0, a0, 32
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; RV64I-LP64E-NEXT: addi a0, a0, 7
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; RV64I-LP64E-NEXT: andi a0, a0, -8
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; RV64I-LP64E-NEXT: sub a0, sp, a0
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; RV64I-LP64E-NEXT: mv sp, a0
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; RV64I-LP64E-NEXT: mv a1, s1
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; RV64I-LP64E-NEXT: call callee
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; RV64I-LP64E-NEXT: addi sp, s0, -64
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; RV64I-LP64E-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
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; RV64I-LP64E-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
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; RV64I-LP64E-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
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; RV64I-LP64E-NEXT: addi sp, sp, 64
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; RV64I-LP64E-NEXT: ret
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%1 = alloca i8, i32 %n
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%2 = alloca i32, align 64
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call void @callee(ptr %1, ptr %2)
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ret void
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}
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