llvm-project/llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
Maciej Gabka 95d2d1cba0
Move stepvector intrinsic out of experimental namespace (#98043)
This patch is moving out stepvector intrinsic from the experimental
namespace.

This intrinsic exists in LLVM for several years now, and is widely used.
2024-08-28 12:48:20 +01:00

26 lines
918 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv64 -mattr +v -filetype asm -o - %s | FileCheck %s
declare i8 @llvm.vscale.i8()
declare <vscale x 8 x i8> @llvm.stepvector.nxv8i8()
define <vscale x 8 x i8> @f() #0 {
; CHECK-LABEL: f:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vx v8, v8, a0
; CHECK-NEXT: ret
entry:
%0 = tail call i8 @llvm.vscale.i8()
%1 = shl i8 %0, 3
%.splat.insert = insertelement <vscale x 8 x i8> poison, i8 %1, i64 0
%.splat = shufflevector <vscale x 8 x i8> %.splat.insert, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%2 = tail call <vscale x 8 x i8> @llvm.stepvector.nxv8i8()
%3 = add <vscale x 8 x i8> %2, %.splat
ret <vscale x 8 x i8> %3
}
attributes #0 = { vscale_range(2,1024) }