9375962ac9
The vast majority of the following (very common) opcodes were always called with identical arguments: - `GIM_CheckType` for the root - `GIM_CheckRegBankForClass` for the root - `GIR_Copy` between the old and new root - `GIR_ConstrainSelectedInstOperands` on the new root - `GIR_BuildMI` to create the new root I added overloaded version of each opcode specialized for the root instructions. It always saves between 1 and 2 bytes per instance depending on the number of arguments specialized into the opcode. Some of these opcodes had between 5 and 15k occurences in the AArch64 GlobalISel Match Table. Additionally, the following opcodes are almost always used in the same sequence: - `GIR_EraseFromParent 0` + `GIR_Done` - `GIR_EraseRootFromParent_Done` has been created to do both. Saves 2 bytes per occurence. - `GIR_IsSafeToFold` was *always* called for each InsnID except 0. - Changed the opcode to take the number of instructions to check after `MI[0]` The savings from these are pretty neat. For `AArch64GenGlobalISel.inc`: - `AArch64InstructionSelector.cpp.o` goes down from 772kb to 704kb (-10% code size) - Self-reported MatchTable size goes from 420380 bytes to 352426 bytes (~ -17%) A smaller match table means a faster match table because we spend less time iterating and decoding. I don't have a solid measurement methodology for GlobalISel performance so I don't have precise numbers but I saw a few % of improvements in a simple testcase.
153 lines
8.3 KiB
TableGen
153 lines
8.3 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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// Test the generation of patterns with multiple output operands and makes sure that
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// we are able to create a new instruction if necessary, or just simply change the
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// opcode if the input and output operands of the generic instruction are the same
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// as the target-specific instruction
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// Verify that patterns with multiple outputs are translated
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//-----------------------------------------------------------------------------
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// Test where only the opcode is mutated during ISel
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let Constraints = "$ptr_out = $addr" in
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def LDPost : I<(outs GPR32:$val, GPR32:$ptr_out), (ins GPR32:$addr, GPR32:$off), []>;
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def SDTLoadPost : SDTypeProfile<2, 2, [
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SDTCisInt<0>, SDTCisSameAs<1,2>, SDTCisPtrTy<2>, SDTCisInt<3>,
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]>;
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def loadpost : SDNode<"MyTgt::LOADPOST", SDTLoadPost, [
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SDNPHasChain, SDNPMayLoad, SDNPMemOperand
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]>;
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def G_POST_LOAD : MyTargetGenericInstruction{
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let OutOperandList = (outs type0:$val, type1:$ptr_out);
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let InOperandList = (ins type1:$ptr, type2:$off);
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}
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def : GINodeEquiv<G_POST_LOAD, loadpost>;
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def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)),
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(LDPost GPR32:$addr, GPR32:$off)
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>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_POST_LOAD),
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// CHECK-NEXT: // MIs[0] DstI[val]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] DstI[ptr_out]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_p0s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] addr
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] off
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // (loadpost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) => (LDPost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off)
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// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LDPost),
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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//-----------------------------------------------------------------------------
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// Test where a whole new MIR instruction is created during ISel
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def TWO_INS : I<(outs GPR32:$out1, GPR32:$out2), (ins GPR32:$in1, GPR32:$in2), []>;
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def SDTTwoIn : SDTypeProfile<2, 2, [
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SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>
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]>;
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def two_in : SDNode<"MyTgt::TWO_IN", SDTTwoIn, []>;
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def G_TWO_IN : MyTargetGenericInstruction{
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let OutOperandList = (outs type0:$out1, type0:$out2);
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let InOperandList = (ins type0:$in1, type0:$in2);
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}
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def : GINodeEquiv<G_TWO_IN, two_in>;
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// Swap the input operands for an easy way to force the creation of a new instruction
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def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_IN),
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// CHECK-NEXT: // MIs[0] DstI[out1]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] DstI[out2]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] i1
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] i2
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2) => (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1)
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1]
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2]
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // i2
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // i1
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage
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// CHECK-NEXT: GIR_EraseRootFromParent_Done,
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//-----------------------------------------------------------------------------
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// Test where implicit defs are added using Defs.
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let Defs = [R0] in
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def ImplicitDefInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;
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def OtherInstr : I<(outs GPR32:$dst), (ins GPR32:$src), []>;
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def : Pat<(i32 (add i32:$src, i32:$src)),
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(OtherInstr (ImplicitDefInstr GPR32:$src))>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
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// CHECK-NEXT: // MIs[0] DstI[dst]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
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// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (ImplicitDefInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src))
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::ImplicitDefInstr),
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
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// CHECK-NEXT: GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for MyTarget::R0*/0,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage
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// CHECK-NEXT: GIR_EraseRootFromParent_Done,
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//-----------------------------------------------------------------------------
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// Test when the inner instruction in the output pattern has two outs
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// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD),
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// CHECK-NEXT: // MIs[0] DstI[dst]
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
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// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
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// CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (TwoOutsInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src))
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::TwoOutsInstr),
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
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// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr),
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// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
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// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
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// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands,
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// CHECK-NEXT: // GIR_Coverage
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// CHECK-NEXT: GIR_EraseRootFromParent_Done,
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def TwoOutsInstr : I<(outs GPR32:$out1, GPR32:$out2), (ins GPR32:$src), []>;
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def : Pat<(i32 (add i32:$src, i32:$src)),
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(OtherInstr (TwoOutsInstr GPR32:$src))>;
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