43fd244b3d
(with fix for ubsan) This enables the --lto-partitions option to work more consistently. This module splitting logic is fully aware of AMDGPU modules and their specificities and takes advantage of them to split modules in a way that avoids compilation issue (such as resource usage being incorrectly represented). This also includes a logging system that's more elaborate than just LLVM_DEBUG which allows printing logs to uniquely named files, and optionally with all value names hidden so they can be safely shared without leaking informatiton about the source. Logs can also be enabled through an environment variable, which avoids the sometimes complicated process of passing a -mllvm option all the way from clang driver to the offload linker that handles full LTO codegen.
76 lines
1.7 KiB
LLVM
76 lines
1.7 KiB
LLVM
; RUN: llvm-split -o %t %s -j 3 -mtriple amdgcn-amd-amdhsa
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; RUN: llvm-dis -o - %t0 | FileCheck --check-prefix=CHECK0 %s
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; RUN: llvm-dis -o - %t1 | FileCheck --check-prefix=CHECK1 %s
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; RUN: llvm-dis -o - %t2 | FileCheck --check-prefix=CHECK2 %s
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; Test load balancing logic with 6 kernels.
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;
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; Kernels go from most expensive (A == 6) to least expensive (F == 1)
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;
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; Load balancing should work like this (current partition cost is in parens)
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;
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; Initial -> [P0(0), P1(0), P2(0)]
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;
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; A(6) goes in 2 -> [P2(6), P0(0), P1(0)]
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; B(5) goes in 1 -> [P2(6), P1(5), P0(4)]
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; C(4) goes in 0 -> [P2(6), P1(5), P0(4)]
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; D(3) goes in 0 -> [P0(7), P2(6), P1(5)]
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; E(2) goes in 1 -> [P0(7), P1(7), P2(6)]
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; F(1) goes in 2 -> [P0(7), P1(7), P2(7)]
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; CHECK0-NOT: define
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; CHECK0: define amdgpu_kernel void @C
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; CHECK0: define amdgpu_kernel void @D
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; CHECK0-NOT: define
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; CHECK1-NOT: define
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; CHECK1: define amdgpu_kernel void @B
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; CHECK1: define amdgpu_kernel void @E
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; CHECK1-NOT: define
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; CHECK2-NOT: define
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; CHECK2: define amdgpu_kernel void @A
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; CHECK2: define amdgpu_kernel void @F
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; CHECK2-NOT: define
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define amdgpu_kernel void @A(ptr %x) {
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store i64 42, ptr %x
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store i64 43, ptr %x
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store i64 44, ptr %x
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store i64 45, ptr %x
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store i64 46, ptr %x
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ret void
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}
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define amdgpu_kernel void @B(ptr %x) {
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store i64 42, ptr %x
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store i64 43, ptr %x
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store i64 44, ptr %x
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store i64 45, ptr %x
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ret void
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}
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define amdgpu_kernel void @C(ptr %x) {
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store i64 42, ptr %x
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store i64 43, ptr %x
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store i64 44, ptr %x
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ret void
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}
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define amdgpu_kernel void @D(ptr %x) {
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store i64 42, ptr %x
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store i64 43, ptr %x
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ret void
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}
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define amdgpu_kernel void @E(ptr %x) {
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store i64 42, ptr %x
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ret void
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}
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define amdgpu_kernel void @F() {
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ret void
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}
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