538aeb180b
Previously, we always used the wave64 encodings for EH registers regardless of whether we were compiling for wave32, which seems wrong. We don't seem to use the EH registers, so this commit is mostly just about papering over code that converts from non-EH dwarf registers to LLVM registers while claiming they are EH dwarf registers. That kind of code should be okay on any non-darwin target (since darwin is the only target that uses a different encoding for EH registers).
62 lines
2.4 KiB
C++
62 lines
2.4 KiB
C++
//===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUUnitTests.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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TEST(AMDGPU, TestWave64DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave64 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
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// A0 => 3072, A255 => 3327
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for (int llvmReg :
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{16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
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MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
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}
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}
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}
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}
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}
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TEST(AMDGPU, TestWave32DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave32 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
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// A0 => 2048, A255 => 2303
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for (int llvmReg :
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{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
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MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
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EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, true));
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}
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}
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}
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}
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}
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