123064dc39
This cc1 option -fallow-half-arguments-and-returns allows __fp16 to be passed by argument and returned, without giving an error. It is currently always enabled for Arm and AArch64, by forcing the option in the driver. This means any cc1 tests (especially those needing arm_neon.h) need to specify the option too, to prevent the error from being emitted. This changes it to a target option instead, set to true for Arm and AArch64. This allows the option to be removed. Previously it was implied by -fnative_half_arguments_and_returns, which is set for certain languages like open_cl, renderscript and hlsl, so that option now too controls the errors. There were are few other non-arm uses of -fallow-half-arguments-and-returns but I believe they were unnecessary. The strictfp_builtins.c tests were converted from __fp16 to _Float16 to avoid the issues. Differential Revision: https://reviews.llvm.org/D133885
52 lines
2.3 KiB
C
52 lines
2.3 KiB
C
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -target-abi aapcs -ffreestanding -emit-llvm -w -o - %s | FileCheck %s
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// AAPCS clause C.8 says: If the argument has an alignment of 16 then the NGRN
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// is rounded up to the next even number.
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// CHECK: void @test1(i32 noundef %x0, i128 noundef %x2_x3, i128 noundef %x4_x5, i128 noundef %x6_x7, i128 %sp.coerce)
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typedef union { __int128 a; } Small;
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void test1(int x0, __int128 x2_x3, __int128 x4_x5, __int128 x6_x7, Small sp) {
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}
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// CHECK: void @test2(i32 noundef %x0, i128 %x2_x3.coerce, i32 noundef %x4, i128 %x6_x7.coerce, i32 noundef %sp, i128 %sp16.coerce)
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void test2(int x0, Small x2_x3, int x4, Small x6_x7, int sp, Small sp16) {
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}
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// We coerce HFAs into a contiguous [N x double] type if they're going on the
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// stack in order to avoid holes. Make sure we get all of them, and not just the
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// first:
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// CHECK: void @test3([4 x float] %s0_s3.coerce, float noundef %s4, [4 x float] %sp.coerce, [4 x float] %sp16.coerce)
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typedef struct { float arr[4]; } HFA;
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void test3(HFA s0_s3, float s4, HFA sp, HFA sp16) {
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}
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// However, we shouldn't perform the [N x double] coercion on types which have
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// sufficient alignment to avoid holes on their own. We could coerce to [N x
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// fp128] or something, but leaving them as-is retains more information for
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// users to debug.
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// CHECK: void @test4([3 x <16 x i8>] %v0_v2.coerce, [3 x <16 x i8>] %v3_v5.coerce, [3 x <16 x i8>] %sp.coerce, double noundef %sp48, [3 x <16 x i8>] %sp64.coerce)
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typedef __attribute__((neon_vector_type(16))) signed char int8x16_t;
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typedef struct { int8x16_t arr[3]; } BigHFA;
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void test4(BigHFA v0_v2, BigHFA v3_v5, BigHFA sp, double sp48, BigHFA sp64) {
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}
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// It's the job of the argument *consumer* to perform the required sign & zero
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// extensions under AAPCS. There shouldn't be
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// CHECK: define{{.*}} i8 @test5(i8 noundef %a, i16 noundef %b)
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unsigned char test5(unsigned char a, signed short b) {
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}
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// __fp16 can be used as a function argument or return type (ACLE 2.0)
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// CHECK: define{{.*}} half @test_half(half noundef %{{.*}})
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__fp16 test_half(__fp16 A) { }
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// __fp16 is a base type for homogeneous floating-point aggregates for AArch64 (but not 32-bit ARM).
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// CHECK: define{{.*}} %struct.HFA_half @test_half_hfa([4 x half] %{{.*}})
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struct HFA_half { __fp16 a[4]; };
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struct HFA_half test_half_hfa(struct HFA_half A) { }
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