a41cb8bf58
Unswitching adjusts the CFG in ways that may invalidate cached loop dispositions. Clear all cached block and loop dispositions during trivial unswitching. The same is already done for non-trivial unswitching. Fixes #58751.
141 lines
4.8 KiB
LLVM
141 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes="loop-mssa(indvars,simple-loop-unswitch<nontrivial>)" -verify-scev -S %s | FileCheck %s
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target datalayout = "n16:32"
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@glob = external global i16, align 1
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; Test case for PR58136.
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define void @test_pr58136(i1 %c.1, i1 %c.2) {
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; CHECK-LABEL: @test_pr58136(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[SRC1:%.*]] = alloca i16, align 2
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; CHECK-NEXT: [[L_3:%.*]] = load i16, ptr [[SRC1]], align 2
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; CHECK-NEXT: [[GLOB_PROMOTED:%.*]] = load i16, ptr @glob, align 2
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; CHECK-NEXT: [[C_1_FR:%.*]] = freeze i1 [[C_1:%.*]]
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; CHECK-NEXT: br i1 [[C_1_FR]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY_SPLIT:%.*]]
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; CHECK: entry.split.us:
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; CHECK-NEXT: [[C_2_FR:%.*]] = freeze i1 [[C_2:%.*]]
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; CHECK-NEXT: br i1 [[C_2_FR]], label [[ENTRY_SPLIT_US_SPLIT_US:%.*]], label [[ENTRY_SPLIT_US_SPLIT:%.*]]
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; CHECK: entry.split.us.split.us:
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; CHECK-NEXT: br label [[LOOP_HEADER_US_US:%.*]]
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; CHECK: loop.header.us.us:
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; CHECK-NEXT: [[MUL1_US_US:%.*]] = phi i16 [ [[MUL_US_US:%.*]], [[LOOP_LATCH_US_US:%.*]] ], [ [[GLOB_PROMOTED]], [[ENTRY_SPLIT_US_SPLIT_US]] ]
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; CHECK-NEXT: [[CALL2_US_US:%.*]] = call i16 @foo()
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; CHECK-NEXT: br label [[THEN_BB_US_US:%.*]]
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; CHECK: then.bb.us.us:
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; CHECK-NEXT: br label [[LOOP_LATCH_US_US]]
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; CHECK: loop.latch.us.us:
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; CHECK-NEXT: [[MUL_US_US]] = mul nsw i16 [[MUL1_US_US]], [[L_3]]
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; CHECK-NEXT: store i16 [[MUL_US_US]], ptr @glob, align 2
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; CHECK-NEXT: br label [[LOOP_HEADER_US_US]]
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; CHECK: entry.split.us.split:
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; CHECK-NEXT: br label [[LOOP_HEADER_US:%.*]]
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; CHECK: loop.header.us:
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; CHECK-NEXT: [[CALL2_US:%.*]] = call i16 @foo()
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; CHECK-NEXT: br label [[THEN_BB_US:%.*]]
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; CHECK: then.bb.us:
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; CHECK-NEXT: br label [[EXIT_SPLIT_US:%.*]]
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; CHECK: exit.split.us:
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
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; CHECK: loop.header:
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; CHECK-NEXT: [[CALL2:%.*]] = call i16 @foo()
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; CHECK-NEXT: br label [[EXIT_SPLIT:%.*]]
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; CHECK: exit.split:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%src1 = alloca i16, align 2
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%l.3 = load i16, ptr %src1, align 2
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%glob.promoted = load i16, ptr @glob, align 2
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br label %loop.header
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loop.header: ; preds = %loop.latch, %entry
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%mul1 = phi i16 [ %mul, %loop.latch ], [ %glob.promoted, %entry ]
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%call2 = call i16 @foo()
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br i1 %c.1, label %then.bb, label %exit
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then.bb: ; preds = %loop.header
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br i1 %c.2, label %loop.latch, label %exit
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loop.latch: ; preds = %then.bb
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%mul = mul nsw i16 %mul1, %l.3
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store i16 %mul, ptr @glob, align 2
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br label %loop.header
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exit: ; preds = %then.bb, %loop.header
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ret void
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}
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declare i16 @foo() nounwind readnone
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define void @test_pr58158(i1 %c.1) {
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; CHECK-LABEL: @test_pr58158(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CALL:%.*]] = tail call i16 @bar()
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; CHECK-NEXT: br i1 [[C_1:%.*]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY_SPLIT:%.*]]
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; CHECK: entry.split.us:
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; CHECK-NEXT: br label [[OUTER_US:%.*]]
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; CHECK: outer.us:
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; CHECK-NEXT: br label [[INNER_PREHEADER_US:%.*]]
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; CHECK: inner.us:
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; CHECK-NEXT: [[C_2_US:%.*]] = icmp eq i16 0, [[CALL]]
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; CHECK-NEXT: br i1 [[C_2_US]], label [[OUTER_LOOPEXIT_US:%.*]], label [[INNER_US:%.*]]
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; CHECK: inner.preheader.us:
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; CHECK-NEXT: br label [[INNER_US]]
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; CHECK: outer.loopexit.us:
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; CHECK-NEXT: br label [[OUTER_BACKEDGE_US:%.*]]
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; CHECK: outer.backedge.us:
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; CHECK-NEXT: br label [[OUTER_US]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[OUTER:%.*]]
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; CHECK: outer:
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; CHECK-NEXT: br label [[OUTER_BACKEDGE:%.*]]
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; CHECK: outer.backedge:
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; CHECK-NEXT: br label [[OUTER]]
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;
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entry:
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%call = tail call i16 @bar()
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br label %outer
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outer:
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br i1 %c.1, label %inner, label %outer
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inner:
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%c.2 = icmp eq i16 0, %call
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br i1 %c.2, label %outer, label %inner
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}
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declare i16 @bar()
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define void @pr58751(i16 %a, ptr %dst) {
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entry:
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%c.1 = icmp eq i16 %a, 0
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br label %outer.header
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outer.header:
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%outer.iv = phi i16 [ %a, %entry ], [ %outer.iv.next, %outer.latch ]
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br label %inner.header
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inner.header:
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%inner.iv = phi i16 [ %outer.iv, %outer.header ], [ %inner.iv.next, %inner.latch ]
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br i1 %c.1, label %outer.latch, label %inner.latch
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inner.latch:
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%inner.iv.next = add nsw i16 %inner.iv, 1
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store i16 %inner.iv.next, ptr %dst, align 1
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%c.2 = icmp eq i16 %inner.iv.next, 0
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br i1 %c.2, label %exit, label %inner.header
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outer.latch:
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%outer.iv.next = add nsw i16 %outer.iv, 1
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br label %outer.header
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exit:
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ret void
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}
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