Craig Topper ccb38c5588 Test case for r204305. ...

llvm-svn: 204316

2014-03-20 06:45:10 +00:00

..

avx-512.txt

AVX-512: decoder for AVX-512, made by Alexey Bader.

2013-12-25 11:40:51 +00:00

fp-stack.txt

Add two fp test cases I missed in my previous commit.

2013-12-31 23:15:19 +00:00

hex-immediates.txt

Added a option to the disassembler to print immediates as hex.

2012-12-05 18:13:19 +00:00

intel-syntax-32.txt

First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.

2013-08-25 22:23:38 +00:00

intel-syntax.txt

Fixing Intel format of the vshufpd instruction.

2013-09-27 01:44:23 +00:00

invalid-cmp-imm.txt

Convert the uses of '|&' to use '2>&1 |' instead, which works on old

2012-07-02 18:37:59 +00:00

invalid-VEX-vvvv.txt

Convert the uses of '|&' to use '2>&1 |' instead, which works on old

2012-07-02 18:37:59 +00:00

lit.local.cfg

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

marked-up.txt

Add support for annotated disassembly output for X86 and arm.

2012-10-22 22:31:46 +00:00

missing-sib.txt

Test case for r204305.

2014-03-20 06:45:10 +00:00

moffs.txt

[x86] Fix disassembly of MOV16ao16 et al.

2014-01-20 12:02:53 +00:00

padlock.txt

Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.

2014-02-19 05:34:21 +00:00

prefixes.txt

Fixed a bug where diassembling an instruction that had a prefix would cause LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode.

2013-08-30 21:19:48 +00:00

simple-tests.txt

Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.

2014-01-01 15:29:32 +00:00

truncated-input.txt

Convert the uses of '|&' to use '2>&1 |' instead, which works on old

2012-07-02 18:37:59 +00:00

x86-16.txt

[x86] Fix 16-bit disassembly of JCXZ/JECXZ

2014-01-20 12:02:48 +00:00

x86-32.txt

Add opcode extension forms of MOV8ri/MOV16ri/MOV32ri.

2014-02-15 07:29:18 +00:00

x86-64.txt

Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.

2014-02-17 10:03:43 +00:00