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llvm-project/llvm/lib/Target/RISCV
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Dmitrii Petrov c86a878e89 [RISCV] Add Syntacore SCR1 CPU model 
SCR1 is available at https://github.com/syntacore/scr1

'syntacore-scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'syntacore-scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.

SCR1_CFG_RV32EC_MIN is RV32EC, which is currently unsupported.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139302
2022-12-14 11:45:44 +03:00
..
AsmParser
[RISCV] Add accessors to RISCVMatInt::Inst.
2022-12-07 19:02:01 -08:00
Disassembler
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
GISel
[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
2022-11-15 14:24:50 -08:00
MCA
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
2022-11-18 09:55:15 -08:00
MCTargetDesc
[RISCV] Use bseti for 2048 in RISCVMatInt when Zbs is enabled.
2022-12-07 20:14:22 -08:00
TargetInfo
[RISCV] Re-enable JIT support
2022-08-11 11:41:02 +02:00
CMakeLists.txt
[RISCV][llvm-mca] Use LMUL Instruments to provide more accurate reports on RISCV
2022-11-18 09:55:15 -08:00
RISCV.h
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCV.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVAsmPrinter.cpp
[RISC-V][HWASAN] Fold variable into assert
2022-08-29 00:32:37 +02:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool.
2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Avoid redundant branch-to-branch when expanding cmpxchg
2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp
re-land [RISC-V][HWASAN] Support tagging global variables for RISC-V HWASAN
2022-12-13 15:51:51 +03:00
RISCVFrameLowering.cpp
[RISCV] Generate .cfi_def_cfa_expression for RVV stack adjustment
2022-12-06 12:45:59 +03:00
RISCVFrameLowering.h
[RISCV] Inline RISCVFrameLowering::adjustReg out of existance [nfc]
2022-11-30 11:07:45 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Use std::optional in RISCVGatherScatterLowering.cpp (NFC)
2022-11-25 22:59:57 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Use make_range instead of iterator_range for code from 8e6c3094
2022-12-13 11:17:59 -08:00
RISCVInstrFormats.td
[RISCV] Define custom-N opcodes
2022-11-04 10:05:30 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Replace hardcoded constant with OPIVI.Value in tablegen. NFC
2022-11-30 20:58:40 -08:00
RISCVInstrInfo.cpp
[RISCV] Add accessors to RISCVMatInt::Inst.
2022-12-07 19:02:01 -08:00
RISCVInstrInfo.h
[MachineCombiner] Extend reassociation logic to handle inverse instructions
2022-12-07 13:50:28 +03:00
RISCVInstrInfo.td
[RISCV][NFC] Mark rs1 in most memory instructions as memory operand.
2022-11-22 16:42:44 +03:00
RISCVInstrInfoA.td
[RISCV] Add target feature to force-enable atomics
2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td
Add MC support of RISCV Zcd Extension
2022-11-24 05:48:06 +08:00
RISCVInstrInfoD.td
[RISCV] Inline scalar ceil/floor/trunc/rint/round/roundeven.
2022-10-26 14:36:49 -07:00
RISCVInstrInfoF.td
[RISCV] Add correct predicate over FMV instructions
2022-12-02 13:45:57 +03:00
RISCVInstrInfoM.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions
2022-12-06 16:57:35 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove pseudos for whole register load, store, and move.
2022-12-07 10:19:58 -08:00
RISCVInstrInfoVSDPatterns.td
[DAGCombiner] Scalarize extend/truncate for splat vector.
2022-12-12 14:53:10 +08:00
RISCVInstrInfoVVLPatterns.td
[VP][RISCV] Add vp.nearbyint and RISC-V support.
2022-11-16 14:05:35 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Implement assembler support for XVentanaCondOps
2022-11-14 09:01:54 -08:00
RISCVInstrInfoZb.td
[RISCV] Add isel patterns to select slli+shXadd.uw.
2022-11-21 09:32:51 -08:00
RISCVInstrInfoZfh.td
[RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64 nodes.
2022-12-07 12:25:30 -08:00
RISCVInstrInfoZicbo.td
[RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td
2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
…
RISCVISelDAGToDAG.cpp
[RISCV] Add accessors to RISCVMatInt::Inst.
2022-12-07 19:02:01 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add isel patterns to select slli+shXadd.uw.
2022-11-21 09:32:51 -08:00
RISCVISelLowering.cpp
[VP][RISCV] Add vp.ctpop and RISC-V support.
2022-12-14 09:47:44 +08:00
RISCVISelLowering.h
[DAGCombiner] Scalarize extend/truncate for splat vector.
2022-12-12 14:53:10 +08:00
RISCVMachineFunctionInfo.cpp
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments.
2022-10-04 15:39:10 -07:00
RISCVMacroFusion.cpp
[RISCV] Be more strict about LUI+ADDI macrofusion pre-RA.
2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
RISCVMCInstLower.cpp
[RISCV] Pre-RA expand pseudos pass
2022-07-31 23:19:00 +02:00
RISCVMergeBaseOffset.cpp
[RISCV] Use std::optional in RISCVMergeBaseOffset.cpp (NFC)
2022-11-25 23:08:26 -08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Use analyzeBranch in RISCVRedundantCopyElimination.
2022-08-29 09:05:53 -07:00
RISCVRegisterInfo.cpp
[RISCV] Replace uses of hasStdExtC with COrZca.
2022-12-07 09:34:01 -08:00
RISCVRegisterInfo.h
[RISCV] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex.
2022-12-06 15:42:00 -08:00
RISCVRegisterInfo.td
[RISCV][NFC] Define variables for vector VT list of different LMUL
2022-12-12 10:45:30 +08:00
RISCVSchedRocket.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSiFive7.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Add Syntacore SCR1 CPU model
2022-12-14 11:45:44 +03:00
RISCVSchedule.td
[RISCV] Merge WriteLDW and WriteLDWU schedule classes.
2022-10-28 11:57:33 -07:00
RISCVScheduleV.td
[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions
2022-12-06 16:57:35 -08:00
RISCVScheduleZb.td
[RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC
2022-09-23 21:38:42 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Add support for call returns to RISCVSExtWRemoval.
2022-12-13 09:09:13 -08:00
RISCVSubtarget.cpp
[RISCV] Move GlobalISEL specific files to sub-directory [nfc]
2022-11-15 14:24:50 -08:00
RISCVSubtarget.h
[RISCV] Simplify RISCVSubtarget. NFC
2022-12-09 16:26:16 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Enable the Machine Late Cleanup pass.
2022-12-11 20:55:05 -08:00
RISCVTargetMachine.h
CodeGen/CommandFlags: Convert Optional to std::optional
2022-12-03 18:38:12 +00:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[VP][RISCV] Add vp.ctpop and RISC-V support.
2022-12-14 09:47:44 +08:00
RISCVTargetTransformInfo.h
[RISCV] Codegen support for Zfhmin.
2022-12-06 22:14:15 -08:00