256 lines
9.7 KiB
C++
256 lines
9.7 KiB
C++
//===- X86SuppressAPXForReloc.cpp - Suppress APX features for relocations -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This pass is added to suppress APX features for relocations. It's used to
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/// keep backward compatibility with old version of linker having no APX
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/// support. It can be removed after APX support is included in the default
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/// linker on OS.
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///
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-suppress-apx-for-relocation"
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cl::opt<bool> X86EnableAPXForRelocation(
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"x86-enable-apx-for-relocation",
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cl::desc("Enable APX features (EGPR, NDD and NF) for instructions with "
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"relocations on x86-64 ELF"),
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cl::init(false));
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namespace {
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class X86SuppressAPXForRelocationPass : public MachineFunctionPass {
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public:
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X86SuppressAPXForRelocationPass() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "X86 Suppress APX features for relocation";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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static char ID;
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};
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} // namespace
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char X86SuppressAPXForRelocationPass::ID = 0;
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INITIALIZE_PASS_BEGIN(X86SuppressAPXForRelocationPass, DEBUG_TYPE,
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"X86 Suppress APX features for relocation", false, false)
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INITIALIZE_PASS_END(X86SuppressAPXForRelocationPass, DEBUG_TYPE,
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"X86 Suppress APX features for relocation", false, false)
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FunctionPass *llvm::createX86SuppressAPXForRelocationPass() {
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return new X86SuppressAPXForRelocationPass();
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}
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static void suppressEGPRRegClass(MachineRegisterInfo *MRI, MachineInstr &MI,
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const X86Subtarget &ST, unsigned int OpNum) {
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Register Reg = MI.getOperand(OpNum).getReg();
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if (!Reg.isVirtual()) {
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assert(!X86II::isApxExtendedReg(Reg) && "APX EGPR is used unexpectedly.");
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return;
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}
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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const X86RegisterInfo *RI = ST.getRegisterInfo();
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const TargetRegisterClass *NewRC = RI->constrainRegClassToNonRex2(RC);
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MRI->setRegClass(Reg, NewRC);
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}
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// Suppress EGPR in operand 0 of uses to avoid APX relocation types emitted. The
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// register in operand 0 of instruction with relocation may be replaced with
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// operand 0 of uses which may be EGPR. That may lead to emit APX relocation
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// types which breaks the backward compatibility with builtin linkers on
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// existing OS. For example, the register in operand 0 of instruction with
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// relocation is used in PHI instruction, and it may be replaced with operand 0
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// of PHI instruction after PHI elimination and Machine Copy Propagation pass.
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static void suppressEGPRRegClassInRegAndUses(MachineRegisterInfo *MRI,
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MachineInstr &MI,
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const X86Subtarget &ST,
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unsigned int OpNum) {
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suppressEGPRRegClass(MRI, MI, ST, OpNum);
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Register Reg = MI.getOperand(OpNum).getReg();
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for (MachineInstr &Use : MRI->use_instructions(Reg))
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if (Use.getOpcode() == X86::PHI)
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suppressEGPRRegClass(MRI, Use, ST, 0);
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}
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static bool handleInstructionWithEGPR(MachineFunction &MF,
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const X86Subtarget &ST) {
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if (!ST.hasEGPR())
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return false;
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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auto suppressEGPRInInstrWithReloc = [&](MachineInstr &MI,
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ArrayRef<unsigned> OpNoArray) {
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int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
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X86II::getOperandBias(MI.getDesc());
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const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
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if (MO.getTargetFlags() == X86II::MO_GOTTPOFF ||
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MO.getTargetFlags() == X86II::MO_GOTPCREL) {
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LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
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<< MI);
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for (unsigned OpNo : OpNoArray)
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suppressEGPRRegClassInRegAndUses(MRI, MI, ST, OpNo);
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LLVM_DEBUG(dbgs() << "to:\n " << MI << "\n");
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}
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};
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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// For GOTPC32_TLSDESC, it's emitted with physical register (EAX/RAX) in
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// X86AsmPrinter::LowerTlsAddr, and there is no corresponding target
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// flag for it, so we don't need to handle LEA64r with TLSDESC and EGPR
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// in this pass (before emitting assembly).
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case X86::TEST32mr:
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case X86::TEST64mr: {
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suppressEGPRInInstrWithReloc(MI, {5});
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break;
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}
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case X86::CMP32rm:
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case X86::CMP64rm:
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case X86::MOV32rm:
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case X86::MOV64rm: {
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suppressEGPRInInstrWithReloc(MI, {0});
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break;
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}
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case X86::ADC32rm:
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case X86::ADD32rm:
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case X86::AND32rm:
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case X86::OR32rm:
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case X86::SBB32rm:
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case X86::SUB32rm:
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case X86::XOR32rm:
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case X86::ADC64rm:
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case X86::ADD64rm:
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case X86::AND64rm:
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case X86::OR64rm:
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case X86::SBB64rm:
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case X86::SUB64rm:
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case X86::XOR64rm: {
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suppressEGPRInInstrWithReloc(MI, {0, 1});
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break;
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}
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}
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}
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}
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return true;
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}
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static bool handleNDDOrNFInstructions(MachineFunction &MF,
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const X86Subtarget &ST) {
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if (!ST.hasNDD() && !ST.hasNF())
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return false;
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const X86InstrInfo *TII = ST.getInstrInfo();
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case X86::ADD64rm_NF:
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case X86::ADD64mr_NF_ND:
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case X86::ADD64rm_NF_ND: {
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int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
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X86II::getOperandBias(MI.getDesc());
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const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
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if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
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llvm_unreachable("Unexpected NF instruction!");
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break;
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}
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case X86::ADD64rm_ND: {
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int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
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X86II::getOperandBias(MI.getDesc());
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const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
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if (MO.getTargetFlags() == X86II::MO_GOTTPOFF ||
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MO.getTargetFlags() == X86II::MO_GOTPCREL) {
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LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
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<< MI);
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Register Reg = MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);
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[[maybe_unused]] MachineInstrBuilder CopyMIB =
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
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Reg)
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.addReg(MI.getOperand(1).getReg());
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MI.getOperand(1).setReg(Reg);
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const MCInstrDesc &NewDesc = TII->get(X86::ADD64rm);
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MI.setDesc(NewDesc);
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suppressEGPRRegClassInRegAndUses(MRI, MI, ST, 0);
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MI.tieOperands(0, 1);
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LLVM_DEBUG(dbgs() << "to:\n " << *CopyMIB << "\n");
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LLVM_DEBUG(dbgs() << " " << MI << "\n");
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}
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break;
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}
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case X86::ADD64mr_ND: {
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int MemRefBegin = X86II::getMemoryOperandNo(MI.getDesc().TSFlags);
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const MachineOperand &MO = MI.getOperand(MemRefBegin + X86::AddrDisp);
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if (MO.getTargetFlags() == X86II::MO_GOTTPOFF) {
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LLVM_DEBUG(dbgs() << "Transform instruction with relocation type:\n "
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<< MI);
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suppressEGPRRegClassInRegAndUses(MRI, MI, ST, 0);
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Register Reg = MRI->createVirtualRegister(&X86::GR64_NOREX2RegClass);
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[[maybe_unused]] MachineInstrBuilder CopyMIB =
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
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Reg)
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.addReg(MI.getOperand(6).getReg());
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MachineInstrBuilder NewMIB =
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(X86::ADD64rm),
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MI.getOperand(0).getReg())
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.addReg(Reg)
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.addReg(MI.getOperand(1).getReg())
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.addImm(MI.getOperand(2).getImm())
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.addReg(MI.getOperand(3).getReg())
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.add(MI.getOperand(4))
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.addReg(MI.getOperand(5).getReg());
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MachineOperand *FlagDef =
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MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr);
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if (FlagDef && FlagDef->isDead()) {
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MachineOperand *NewFlagDef =
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NewMIB->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr);
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if (NewFlagDef)
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NewFlagDef->setIsDead();
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}
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MI.eraseFromParent();
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LLVM_DEBUG(dbgs() << "to:\n " << *CopyMIB << "\n");
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LLVM_DEBUG(dbgs() << " " << *NewMIB << "\n");
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}
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break;
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}
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}
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}
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}
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return true;
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}
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bool X86SuppressAPXForRelocationPass::runOnMachineFunction(
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MachineFunction &MF) {
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if (X86EnableAPXForRelocation)
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return false;
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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bool Changed = handleInstructionWithEGPR(MF, ST);
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Changed |= handleNDDOrNFInstructions(MF, ST);
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return Changed;
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}
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