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llvm-project/llvm/test/CodeGen
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Anna Thomas b2195bc771 [SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM 
The missing legalization in SelectionDAG was identified when adding the
intrinsic support for vector reduction for maximum/minimum (D152370).

Fixes part of PR: https://github.com/llvm/llvm-project/issues/63267

Differential Revision: https://reviews.llvm.org/D152718
2023-06-12 12:22:21 -04:00
..
AArch64
[SelectionDAG][AArch64] Legalize FMAXIMUM/FMINIMUM
2023-06-12 12:22:21 -04:00
AMDGPU
[AMDGPU] Fix resource-usage-pal.ll
2023-06-12 08:06:46 -07:00
ARC
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
ARM
[AArch64][ARM][X86] Split XRay tests for Linux/macOS
2023-06-11 12:53:29 -07:00
AVR
[AVR] Optimize 8-bit rotation when rotation bits == 3
2023-06-11 08:41:47 +08:00
BPF
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
CSKY
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
DirectX
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
Generic
…
Hexagon
[RDF] Create individual phi for each indivisible register
2023-06-08 11:07:57 -07:00
Inputs
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
Lanai
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
LoongArch
[LoongArch] Define ual feature and override allowsMisalignedMemoryAccesses
2023-06-07 13:40:58 +08:00
M68k
[m68k] Add TLS Support
2023-06-03 19:09:47 +08:00
Mips
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
MIR
[AMDGPU] Use resource base for buffer instruction MachineMemOperands
2023-06-05 17:06:57 +00:00
MLRegalloc
[NFC][Py Reformat] Reformat python files in llvm
2023-05-17 10:48:52 +02:00
MSP430
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
NVPTX
[NVPTX] Remove few more unneeded fp16 instruction variants
2023-06-09 12:09:08 -07:00
PowerPC
IR: Add llvm.ldexp and llvm.experimental.constrained.ldexp intrinsics
2023-06-06 17:07:18 -04:00
RISCV
[LegalizeTypes][VP] Widen load/store of fixed length vectors to VP ops
2023-06-12 10:21:04 +01:00
SPARC
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
SPIRV
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
SystemZ
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
Thumb
[IR] Make stack protector symbol dso_local according to -f[no-]direct-access-external-data
2023-05-23 09:49:57 -07:00
Thumb2
Revert "[DAGCombine] Make sure combined nodes are added back to the worklist in topological order."
2023-06-05 10:55:58 -04:00
VE
[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.
2023-05-23 09:19:55 -07:00
WebAssembly
[WebAssembly] Re-land 8392bf6000ad
2023-06-09 08:42:27 -07:00
WinCFGuard
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
WinEH
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
X86
[GlobalIsel][X86] Rename x86_64-select-fcmp.mir to select-fcmp.mir and add 32-bit test coverage
2023-06-12 12:41:27 +01:00
XCore
[XCore] Use backwards scavenging in frame index elimination
2023-05-18 09:58:53 +01:00