b9808e5660
Loop unrolling tends to produce chains of `%x1 = add %x0, 1; %x2 = add %x1, 1; ...` with one add per unrolled iteration. This patch simplifies these adds to `%xN = add %x0, N` directly during unrolling, rather than waiting for InstCombine to do so. The motivation for this is that having a single add (rather than an add chain) on the induction variable makes it a simple recurrence, which we specially recognize in a number of places. This allows InstCombine to directly perform folds with that knowledge, instead of first folding the add chains, and then doing other folds in another InstCombine iteration. Due to the reduced number of InstCombine iterations, this also results in a small compile-time improvement. Differential Revision: https://reviews.llvm.org/D153540
89 lines
4.5 KiB
LLVM
89 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=loop-unroll -unroll-allow-partial %s | FileCheck %s
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; This is a variant on full-unroll-non-latch-exit.ll for partial unrolling.
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; This test is primarily interested in making sure that latches are not
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; folded incorrectly, not that a transform occurs.
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define i1 @test(ptr %a1, ptr %a2) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: start:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[START:%.*]] ], [ [[IV_NEXT_4:%.*]], [[LATCH_4:%.*]] ]
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; CHECK-NEXT: br label [[LATCH:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i64, ptr [[A1:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i64, ptr [[A2:%.*]], i64 [[IV]]
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; CHECK-NEXT: [[LOAD1:%.*]] = load i64, ptr [[GEP1]], align 8
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; CHECK-NEXT: [[LOAD2:%.*]] = load i64, ptr [[GEP2]], align 8
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; CHECK-NEXT: [[EXITCOND2:%.*]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
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; CHECK-NEXT: br i1 [[EXITCOND2]], label [[LOOP_1:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.1:
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; CHECK-NEXT: br label [[LATCH_1:%.*]]
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; CHECK: latch.1:
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; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 2
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; CHECK-NEXT: [[GEP1_1:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT]]
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; CHECK-NEXT: [[GEP2_1:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT]]
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; CHECK-NEXT: [[LOAD1_1:%.*]] = load i64, ptr [[GEP1_1]], align 8
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; CHECK-NEXT: [[LOAD2_1:%.*]] = load i64, ptr [[GEP2_1]], align 8
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; CHECK-NEXT: [[EXITCOND2_1:%.*]] = icmp eq i64 [[LOAD1_1]], [[LOAD2_1]]
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; CHECK-NEXT: br i1 [[EXITCOND2_1]], label [[LOOP_2:%.*]], label [[EXIT]]
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; CHECK: loop.2:
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; CHECK-NEXT: br label [[LATCH_2:%.*]]
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; CHECK: latch.2:
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; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 3
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; CHECK-NEXT: [[GEP1_2:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_1]]
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; CHECK-NEXT: [[GEP2_2:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_1]]
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; CHECK-NEXT: [[LOAD1_2:%.*]] = load i64, ptr [[GEP1_2]], align 8
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; CHECK-NEXT: [[LOAD2_2:%.*]] = load i64, ptr [[GEP2_2]], align 8
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; CHECK-NEXT: [[EXITCOND2_2:%.*]] = icmp eq i64 [[LOAD1_2]], [[LOAD2_2]]
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; CHECK-NEXT: br i1 [[EXITCOND2_2]], label [[LOOP_3:%.*]], label [[EXIT]]
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; CHECK: loop.3:
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; CHECK-NEXT: br label [[LATCH_3:%.*]]
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; CHECK: latch.3:
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; CHECK-NEXT: [[IV_NEXT_3:%.*]] = add nuw nsw i64 [[IV]], 4
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; CHECK-NEXT: [[GEP1_3:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_2]]
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; CHECK-NEXT: [[GEP2_3:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_2]]
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; CHECK-NEXT: [[LOAD1_3:%.*]] = load i64, ptr [[GEP1_3]], align 8
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; CHECK-NEXT: [[LOAD2_3:%.*]] = load i64, ptr [[GEP2_3]], align 8
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; CHECK-NEXT: [[EXITCOND2_3:%.*]] = icmp eq i64 [[LOAD1_3]], [[LOAD2_3]]
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; CHECK-NEXT: br i1 [[EXITCOND2_3]], label [[LOOP_4:%.*]], label [[EXIT]]
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; CHECK: loop.4:
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; CHECK-NEXT: [[EXITCOND_4:%.*]] = icmp eq i64 [[IV_NEXT_3]], 24
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; CHECK-NEXT: br i1 [[EXITCOND_4]], label [[EXIT]], label [[LATCH_4]]
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; CHECK: latch.4:
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; CHECK-NEXT: [[IV_NEXT_4]] = add nuw nsw i64 [[IV]], 5
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; CHECK-NEXT: [[GEP1_4:%.*]] = getelementptr inbounds i64, ptr [[A1]], i64 [[IV_NEXT_3]]
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; CHECK-NEXT: [[GEP2_4:%.*]] = getelementptr inbounds i64, ptr [[A2]], i64 [[IV_NEXT_3]]
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; CHECK-NEXT: [[LOAD1_4:%.*]] = load i64, ptr [[GEP1_4]], align 8
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; CHECK-NEXT: [[LOAD2_4:%.*]] = load i64, ptr [[GEP2_4]], align 8
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; CHECK-NEXT: [[EXITCOND2_4:%.*]] = icmp eq i64 [[LOAD1_4]], [[LOAD2_4]]
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; CHECK-NEXT: br i1 [[EXITCOND2_4]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[EXIT_VAL:%.*]] = phi i1 [ false, [[LATCH]] ], [ false, [[LATCH_1]] ], [ false, [[LATCH_2]] ], [ false, [[LATCH_3]] ], [ true, [[LOOP_4]] ], [ false, [[LATCH_4]] ]
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; CHECK-NEXT: ret i1 [[EXIT_VAL]]
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;
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start:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %start ], [ %iv.next, %latch ]
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%exitcond = icmp eq i64 %iv, 24
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br i1 %exitcond, label %exit, label %latch
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latch:
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%iv.next = add nuw nsw i64 %iv, 1
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%gep1 = getelementptr inbounds i64, ptr %a1, i64 %iv
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%gep2 = getelementptr inbounds i64, ptr %a2, i64 %iv
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%load1 = load i64, ptr %gep1, align 8
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%load2 = load i64, ptr %gep2, align 8
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%exitcond2 = icmp eq i64 %load1, %load2
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br i1 %exitcond2, label %loop, label %exit
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exit:
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%exit.val = phi i1 [ false, %latch ], [ true, %loop ]
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ret i1 %exit.val
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}
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