706e71076e
Some of the tests from the X86 directory can be generalized to improve coverage for other architectures
68 lines
2.8 KiB
LLVM
68 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}
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; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}
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define void @test() {
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; CHECK-LABEL: define void @test() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr null, align 2
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; CHECK-NEXT: [[TMP1:%.*]] = and i8 0, 1
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 0, 0
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; CHECK-NEXT: [[TMP3:%.*]] = select i1 false, i32 0, i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i8> <i8 0, i8 poison, i8 poison, i8 poison>, i8 [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i8> [[TMP5]] to <4 x i1>
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; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP4]], <4 x i8> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i8> [[TMP7]], zeroinitializer
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; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i8> [[TMP8]] to <4 x i1>
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; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i1> zeroinitializer, [[TMP15]]
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <4 x i1> [[TMP9]], [[TMP10]]
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; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP15]] to <4 x i32>
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; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
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; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP13]])
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; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 0, [[TMP14]]
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; CHECK-NEXT: store i32 [[OP_RDX]], ptr null, align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%0 = load i16, ptr null, align 2
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%1 = and i8 0, 1
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%2 = and i32 0, 0
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%3 = select i1 false, i32 0, i32 0
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%i2 = sext i8 %1 to i32
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%i3 = or i8 %1, 0
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%i4 = sext i8 %i3 to i32
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%i5 = or i32 0, %i2
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%b1 = icmp eq i32 %i4, %i5
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%a1 = select i1 %b1, i32 0, i32 0
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%4 = and i32 %a1, 0
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%s1 = and i32 %4, 0
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%i8 = sext i8 %1 to i32
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%i9 = or i8 %1, 0
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%i10 = sext i8 %i9 to i32
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%i11 = or i32 0, %i8
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%b2 = icmp eq i32 %i10, %i11
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%a2 = select i1 %b2, i32 0, i32 0
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%5 = and i32 %a2, 0
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%s2 = and i32 %5, %s1
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%i14 = sext i8 %1 to i32
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%i15 = or i8 %1, 0
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%i16 = sext i8 %i15 to i32
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%i17 = or i32 0, %i14
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%b3 = icmp eq i32 %i16, %i17
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%a3 = select i1 %b3, i32 %i14, i32 0
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%6 = and i32 %a3, 0
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%s3 = and i32 %6, %s2
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%i20 = sext i8 0 to i32
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%i21 = or i8 %1, 0
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%i22 = sext i8 %i21 to i32
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%i23 = or i32 0, %i20
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%b4 = icmp eq i32 %i22, %i23
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%a4 = select i1 %b4, i32 0, i32 0
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%7 = and i32 %a4, 0
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%s4 = and i32 %7, %s3
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store i32 %s4, ptr null, align 4
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ret void
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}
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