9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
101 lines
3.5 KiB
LLVM
101 lines
3.5 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}alignbit_shr_pat:
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; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]
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; GCN-DAG: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
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define amdgpu_kernel void @alignbit_shr_pat(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, ptr addrspace(1) %arg, align 8
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%tmp3 = and i32 %arg2, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_v:
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; GCN-DAG: load_dword v[[SHR:[0-9]+]],
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; GCN-DAG: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
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define amdgpu_kernel void @alignbit_shr_pat_v(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep1 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tid
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%tmp = load i64, ptr addrspace(1) %gep1, align 8
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%gep2 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tid
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%amt = load i32, ptr addrspace(1) %gep2, align 4
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%tmp3 = and i32 %amt, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %gep2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and30:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_and30(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, ptr addrspace(1) %arg, align 8
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%tmp3 = and i32 %arg2, 30
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and63:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_and63(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, ptr addrspace(1) %arg, align 8
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%tmp3 = and i32 %arg2, 63
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_const30:
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; GCN: load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], 30
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define amdgpu_kernel void @alignbit_shr_pat_const30(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {
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bb:
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%tmp = load i64, ptr addrspace(1) %arg, align 8
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%tmp5 = lshr i64 %tmp, 30
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_const33:
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; Negative test, shift amount more than 31
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; GCN: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_const33(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {
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bb:
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%tmp = load i64, ptr addrspace(1) %arg, align 8
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%tmp5 = lshr i64 %tmp, 33
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, ptr addrspace(1) %arg1, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable }
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