9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
28 lines
1.6 KiB
LLVM
28 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
|
|
|
|
declare double @llvm.maxnum.f64(double, double) nounwind readnone
|
|
|
|
; SI-LABEL: {{^}}test_fmax3_f64:
|
|
; SI: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 glc{{$}}
|
|
; SI: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
|
|
; SI: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16
|
|
; SI: v_max_f64 [[QUIET_A:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGA]]
|
|
; SI: v_max_f64 [[QUIET_B:v\[[0-9]+:[0-9]+\]]], [[REGB]], [[REGB]]
|
|
; SI: v_max_f64 [[MAX0:v\[[0-9]+:[0-9]+\]]], [[QUIET_A]], [[QUIET_B]]
|
|
; SI: v_max_f64 [[QUIET_C:v\[[0-9]+:[0-9]+\]]], [[REGC]], [[REGC]]
|
|
; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[MAX0]], [[QUIET_C]]
|
|
; SI: buffer_store_dwordx2 [[RESULT]],
|
|
; SI: s_endpgm
|
|
define amdgpu_kernel void @test_fmax3_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr) nounwind {
|
|
%bptr = getelementptr double, ptr addrspace(1) %aptr, i32 1
|
|
%cptr = getelementptr double, ptr addrspace(1) %aptr, i32 2
|
|
%a = load volatile double, ptr addrspace(1) %aptr, align 8
|
|
%b = load volatile double, ptr addrspace(1) %bptr, align 8
|
|
%c = load volatile double, ptr addrspace(1) %cptr, align 8
|
|
%f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone
|
|
%f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone
|
|
store double %f1, ptr addrspace(1) %out, align 8
|
|
ret void
|
|
}
|