86e02ce2dc
computeKnownBits didn't handle fp_to_fp16 to report the high bits as 0. ARM maps the generic node to an instruction that does not modify the high bits of the register, so introduce a target node where the high bits are known 0. llvm-svn: 297873
81 lines
2.8 KiB
LLVM
81 lines
2.8 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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;RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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;RUN: llc < %s -march=amdgcn | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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;FUNC-LABEL: {{^}}test:
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;EG: EXP_IEEE
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;SI: v_exp_f32
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define void @test(float addrspace(1)* %out, float %in) {
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entry:
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%0 = call float @llvm.exp2.f32(float %in)
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store float %0, float addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}testv2:
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;EG: EXP_IEEE
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;EG: EXP_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;SI: v_exp_f32
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;SI: v_exp_f32
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define void @testv2(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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entry:
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%0 = call <2 x float> @llvm.exp2.v2f32(<2 x float> %in)
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store <2 x float> %0, <2 x float> addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}testv4:
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;EG: EXP_IEEE
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;EG: EXP_IEEE
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;EG: EXP_IEEE
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;EG: EXP_IEEE
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; FIXME: We should be able to merge these packets together on Cayman so we
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; have a maximum of 4 instructions.
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}} (MASKED)
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;CM-DAG: EXP_IEEE T{{[0-9]+\.[XYZW]}}
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;SI: v_exp_f32
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;SI: v_exp_f32
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;SI: v_exp_f32
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;SI: v_exp_f32
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define void @testv4(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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entry:
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%0 = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in)
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store <4 x float> %0, <4 x float> addrspace(1)* %out
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ret void
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}
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declare float @llvm.exp2.f32(float) readnone
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declare <2 x float> @llvm.exp2.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.exp2.v4f32(<4 x float>) readnone
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