bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
96 lines
3.2 KiB
C++
96 lines
3.2 KiB
C++
//===- MCDisassembler.cpp - Disassembler interface ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/ADT/ArrayRef.h"
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using namespace llvm;
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MCDisassembler::~MCDisassembler() = default;
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Optional<MCDisassembler::DecodeStatus>
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MCDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const {
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return None;
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}
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bool MCDisassembler::tryAddingSymbolicOperand(MCInst &Inst, int64_t Value,
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uint64_t Address, bool IsBranch,
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uint64_t Offset, uint64_t OpSize,
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uint64_t InstSize) const {
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if (Symbolizer)
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return Symbolizer->tryAddingSymbolicOperand(Inst, *CommentStream, Value,
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Address, IsBranch, Offset,
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OpSize, InstSize);
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return false;
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}
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void MCDisassembler::tryAddingPcLoadReferenceComment(int64_t Value,
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uint64_t Address) const {
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if (Symbolizer)
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Symbolizer->tryAddingPcLoadReferenceComment(*CommentStream, Value, Address);
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}
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void MCDisassembler::setSymbolizer(std::unique_ptr<MCSymbolizer> Symzer) {
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Symbolizer = std::move(Symzer);
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}
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#define SMC_PCASE(A, P) \
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case XCOFF::XMC_##A: \
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return P;
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static uint8_t getSMCPriority(XCOFF::StorageMappingClass SMC) {
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switch (SMC) {
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SMC_PCASE(PR, 1)
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SMC_PCASE(RO, 1)
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SMC_PCASE(DB, 1)
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SMC_PCASE(GL, 1)
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SMC_PCASE(XO, 1)
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SMC_PCASE(SV, 1)
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SMC_PCASE(SV64, 1)
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SMC_PCASE(SV3264, 1)
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SMC_PCASE(TI, 1)
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SMC_PCASE(TB, 1)
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SMC_PCASE(RW, 1)
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SMC_PCASE(TC0, 0)
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SMC_PCASE(TC, 1)
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SMC_PCASE(TD, 1)
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SMC_PCASE(DS, 1)
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SMC_PCASE(UA, 1)
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SMC_PCASE(BS, 1)
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SMC_PCASE(UC, 1)
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SMC_PCASE(TL, 1)
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SMC_PCASE(UL, 1)
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SMC_PCASE(TE, 1)
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#undef SMC_PCASE
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}
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return 0;
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}
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/// The function is for symbol sorting when symbols have the same address.
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/// The symbols in the same section are sorted in ascending order.
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/// llvm-objdump -D will choose the highest priority symbol to display when
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/// there are symbols with the same address.
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bool XCOFFSymbolInfo::operator<(const XCOFFSymbolInfo &SymInfo) const {
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// Label symbols have higher priority than non-label symbols.
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if (IsLabel != SymInfo.IsLabel)
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return SymInfo.IsLabel;
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// Symbols with a StorageMappingClass have higher priority than those without.
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if (StorageMappingClass.hasValue() != SymInfo.StorageMappingClass.hasValue())
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return SymInfo.StorageMappingClass.hasValue();
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if (StorageMappingClass.hasValue()) {
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return getSMCPriority(StorageMappingClass.getValue()) <
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getSMCPriority(SymInfo.StorageMappingClass.getValue());
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}
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return false;
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}
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