cc5a1b3dd9
MIR support is totally unusable for AMDGPU without this, since the set of reserved registers is set from fields here. Add a clone method to MachineFunctionInfo. This is a subtle variant of the copy constructor that is required if there are any MIR constructs that use pointers. Specifically, at minimum fields that reference MachineBasicBlocks or the MachineFunction need to be adjusted to the values in the new function.
306 lines
11 KiB
C++
306 lines
11 KiB
C++
//===-- ARMMachineFunctionInfo.h - ARM machine function info ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares ARM-specific per-machine-function information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <utility>
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namespace llvm {
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/// ARMFunctionInfo - This class is derived from MachineFunctionInfo and
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/// contains private ARM-specific information for each MachineFunction.
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class ARMFunctionInfo : public MachineFunctionInfo {
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virtual void anchor();
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/// isThumb - True if this function is compiled under Thumb mode.
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/// Used to initialized Align, so must precede it.
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bool isThumb = false;
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/// hasThumb2 - True if the target architecture supports Thumb2. Do not use
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/// to determine if function is compiled under Thumb mode, for that use
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/// 'isThumb'.
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bool hasThumb2 = false;
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/// StByValParamsPadding - For parameter that is split between
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/// GPRs and memory; while recovering GPRs part, when
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/// StackAlignment > 4, and GPRs-part-size mod StackAlignment != 0,
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/// we need to insert gap before parameter start address. It allows to
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/// "attach" GPR-part to the part that was passed via stack.
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unsigned StByValParamsPadding = 0;
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/// ArgsRegSaveSize - Size of the register save area for vararg functions or
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/// those making guaranteed tail calls that need more stack argument space
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/// than is provided by this functions incoming parameters.
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///
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unsigned ArgRegsSaveSize = 0;
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/// ReturnRegsCount - Number of registers used up in the return.
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unsigned ReturnRegsCount = 0;
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/// HasStackFrame - True if this function has a stack frame. Set by
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/// determineCalleeSaves().
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bool HasStackFrame = false;
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/// RestoreSPFromFP - True if epilogue should restore SP from FP. Set by
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/// emitPrologue.
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bool RestoreSPFromFP = false;
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/// LRSpilled - True if the LR register has been for spilled for
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/// any reason, so it's legal to emit an ARM::tBfar (i.e. "bl").
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bool LRSpilled = false;
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/// FramePtrSpillOffset - If HasStackFrame, this records the frame pointer
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/// spill stack offset.
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unsigned FramePtrSpillOffset = 0;
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/// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved
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/// register spills areas. For Mac OS X:
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///
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/// GPR callee-saved (1) : r4, r5, r6, r7, lr
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/// --------------------------------------------
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/// GPR callee-saved (2) : r8, r10, r11
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/// --------------------------------------------
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/// DPR callee-saved : d8 - d15
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///
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/// Also see AlignedDPRCSRegs below. Not all D-regs need to go in area 3.
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/// Some may be spilled after the stack has been realigned.
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unsigned GPRCS1Offset = 0;
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unsigned GPRCS2Offset = 0;
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unsigned DPRCSOffset = 0;
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/// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills
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/// areas.
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unsigned FPCXTSaveSize = 0;
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unsigned GPRCS1Size = 0;
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unsigned GPRCS2Size = 0;
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unsigned DPRCSAlignGapSize = 0;
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unsigned DPRCSSize = 0;
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/// NumAlignedDPRCS2Regs - The number of callee-saved DPRs that are saved in
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/// the aligned portion of the stack frame. This is always a contiguous
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/// sequence of D-registers starting from d8.
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///
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/// We do not keep track of the frame indices used for these registers - they
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/// behave like any other frame index in the aligned stack frame. These
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/// registers also aren't included in DPRCSSize above.
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unsigned NumAlignedDPRCS2Regs = 0;
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unsigned PICLabelUId = 0;
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/// VarArgsFrameIndex - FrameIndex for start of varargs area.
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int VarArgsFrameIndex = 0;
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/// HasITBlocks - True if IT blocks have been inserted.
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bool HasITBlocks = false;
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// Security Extensions
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bool IsCmseNSEntry;
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bool IsCmseNSCall;
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/// CPEClones - Track constant pool entries clones created by Constant Island
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/// pass.
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DenseMap<unsigned, unsigned> CPEClones;
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/// ArgumentStackSize - amount of bytes on stack consumed by the arguments
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/// being passed on the stack
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unsigned ArgumentStackSize = 0;
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/// ArgumentStackToRestore - amount of bytes on stack consumed that we must
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/// restore on return.
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unsigned ArgumentStackToRestore = 0;
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/// CoalescedWeights - mapping of basic blocks to the rolling counter of
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/// coalesced weights.
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DenseMap<const MachineBasicBlock*, unsigned> CoalescedWeights;
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/// True if this function has a subset of CSRs that is handled explicitly via
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/// copies.
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bool IsSplitCSR = false;
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/// Globals that have had their storage promoted into the constant pool.
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SmallPtrSet<const GlobalVariable*,2> PromotedGlobals;
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/// The amount the literal pool has been increasedby due to promoted globals.
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int PromotedGlobalsIncrease = 0;
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/// True if r0 will be preserved by a call to this function (e.g. C++
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/// con/destructors).
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bool PreservesR0 = false;
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/// True if the function should sign its return address.
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bool SignReturnAddress = false;
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/// True if the fucntion should sign its return address, even if LR is not
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/// saved.
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bool SignReturnAddressAll = false;
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/// True if BTI instructions should be placed at potential indirect jump
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/// destinations.
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bool BranchTargetEnforcement = false;
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public:
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ARMFunctionInfo() = default;
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explicit ARMFunctionInfo(MachineFunction &MF);
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MachineFunctionInfo *
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clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
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const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
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const override;
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bool isThumbFunction() const { return isThumb; }
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bool isThumb1OnlyFunction() const { return isThumb && !hasThumb2; }
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bool isThumb2Function() const { return isThumb && hasThumb2; }
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bool isCmseNSEntryFunction() const { return IsCmseNSEntry; }
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bool isCmseNSCallFunction() const { return IsCmseNSCall; }
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unsigned getStoredByValParamsPadding() const { return StByValParamsPadding; }
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void setStoredByValParamsPadding(unsigned p) { StByValParamsPadding = p; }
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unsigned getArgRegsSaveSize() const { return ArgRegsSaveSize; }
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void setArgRegsSaveSize(unsigned s) { ArgRegsSaveSize = s; }
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unsigned getReturnRegsCount() const { return ReturnRegsCount; }
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void setReturnRegsCount(unsigned s) { ReturnRegsCount = s; }
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bool hasStackFrame() const { return HasStackFrame; }
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void setHasStackFrame(bool s) { HasStackFrame = s; }
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bool shouldRestoreSPFromFP() const { return RestoreSPFromFP; }
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void setShouldRestoreSPFromFP(bool s) { RestoreSPFromFP = s; }
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bool isLRSpilled() const { return LRSpilled; }
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void setLRIsSpilled(bool s) { LRSpilled = s; }
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unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; }
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void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; }
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unsigned getNumAlignedDPRCS2Regs() const { return NumAlignedDPRCS2Regs; }
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void setNumAlignedDPRCS2Regs(unsigned n) { NumAlignedDPRCS2Regs = n; }
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unsigned getGPRCalleeSavedArea1Offset() const { return GPRCS1Offset; }
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unsigned getGPRCalleeSavedArea2Offset() const { return GPRCS2Offset; }
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unsigned getDPRCalleeSavedAreaOffset() const { return DPRCSOffset; }
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void setGPRCalleeSavedArea1Offset(unsigned o) { GPRCS1Offset = o; }
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void setGPRCalleeSavedArea2Offset(unsigned o) { GPRCS2Offset = o; }
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void setDPRCalleeSavedAreaOffset(unsigned o) { DPRCSOffset = o; }
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unsigned getFPCXTSaveAreaSize() const { return FPCXTSaveSize; }
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unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; }
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unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; }
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unsigned getDPRCalleeSavedGapSize() const { return DPRCSAlignGapSize; }
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unsigned getDPRCalleeSavedAreaSize() const { return DPRCSSize; }
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void setFPCXTSaveAreaSize(unsigned s) { FPCXTSaveSize = s; }
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void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; }
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void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; }
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void setDPRCalleeSavedGapSize(unsigned s) { DPRCSAlignGapSize = s; }
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void setDPRCalleeSavedAreaSize(unsigned s) { DPRCSSize = s; }
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unsigned getArgumentStackSize() const { return ArgumentStackSize; }
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void setArgumentStackSize(unsigned size) { ArgumentStackSize = size; }
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unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
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void setArgumentStackToRestore(unsigned v) { ArgumentStackToRestore = v; }
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void initPICLabelUId(unsigned UId) {
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PICLabelUId = UId;
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}
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unsigned getNumPICLabels() const {
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return PICLabelUId;
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}
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unsigned createPICLabelUId() {
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return PICLabelUId++;
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}
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int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
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void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
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bool hasITBlocks() const { return HasITBlocks; }
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void setHasITBlocks(bool h) { HasITBlocks = h; }
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bool isSplitCSR() const { return IsSplitCSR; }
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void setIsSplitCSR(bool s) { IsSplitCSR = s; }
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void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx) {
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if (!CPEClones.insert(std::make_pair(CPCloneIdx, CPIdx)).second)
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llvm_unreachable("Duplicate entries!");
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}
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unsigned getOriginalCPIdx(unsigned CloneIdx) const {
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DenseMap<unsigned, unsigned>::const_iterator I = CPEClones.find(CloneIdx);
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if (I != CPEClones.end())
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return I->second;
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else
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return -1U;
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}
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DenseMap<const MachineBasicBlock*, unsigned>::iterator getCoalescedWeight(
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MachineBasicBlock* MBB) {
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auto It = CoalescedWeights.find(MBB);
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if (It == CoalescedWeights.end()) {
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It = CoalescedWeights.insert(std::make_pair(MBB, 0)).first;
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}
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return It;
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}
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/// Indicate to the backend that \c GV has had its storage changed to inside
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/// a constant pool. This means it no longer needs to be emitted as a
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/// global variable.
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void markGlobalAsPromotedToConstantPool(const GlobalVariable *GV) {
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PromotedGlobals.insert(GV);
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}
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SmallPtrSet<const GlobalVariable*, 2>& getGlobalsPromotedToConstantPool() {
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return PromotedGlobals;
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}
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int getPromotedConstpoolIncrease() const {
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return PromotedGlobalsIncrease;
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}
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void setPromotedConstpoolIncrease(int Sz) {
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PromotedGlobalsIncrease = Sz;
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}
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DenseMap<unsigned, unsigned> EHPrologueRemappedRegs;
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DenseMap<unsigned, unsigned> EHPrologueOffsetInRegs;
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void setPreservesR0() { PreservesR0 = true; }
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bool getPreservesR0() const { return PreservesR0; }
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bool shouldSignReturnAddress() const {
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return shouldSignReturnAddress(LRSpilled);
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}
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bool shouldSignReturnAddress(bool SpillsLR) const {
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if (!SignReturnAddress)
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return false;
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if (SignReturnAddressAll)
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return true;
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return SpillsLR;
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}
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bool branchTargetEnforcement() const { return BranchTargetEnforcement; }
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H
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