bed9efed71
MCSymbolizer::tryAddingSymbolicOperand() overloaded the Size parameter to specify either the instruction size or the operand size depending on the architecture. However, for proper symbolic disassembly on X86, we need to know both sizes, as an instruction can have two operands, and the instruction size cannot be reliably calculated based on the operand offset and its size. Hence, split Size into OpSize and InstSize. For X86, the new interface allows to fix a couple of issues: * Correctly adjust the value of PC-relative operands. * Set operand size to zero when the operand is specified implicitly. Differential Revision: https://reviews.llvm.org/D126101
901 lines
37 KiB
C++
901 lines
37 KiB
C++
//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCChecker.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "TargetInfo/HexagonTargetInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstddef>
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#include <cstdint>
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#include <memory>
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#define DEBUG_TYPE "hexagon-disassembler"
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using namespace llvm;
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using namespace Hexagon;
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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/// Hexagon disassembler for all Hexagon platforms.
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class HexagonDisassembler : public MCDisassembler {
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public:
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std::unique_ptr<MCInstrInfo const> const MCII;
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std::unique_ptr<MCInst *> CurrentBundle;
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mutable MCInst const *CurrentExtender;
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HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
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CurrentExtender(nullptr) {}
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DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream, bool &Complete) const;
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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void remapInstruction(MCInst &Instr) const;
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};
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static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
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int64_t Value) {
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MCInstrInfo MCII = *Disassembler.MCII;
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if (!Disassembler.CurrentExtender ||
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MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
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return Value;
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unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
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uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
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int64_t Bits;
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bool Success =
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Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
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Bits);
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assert(Success);
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(void)Success;
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uint64_t Upper26 = static_cast<uint64_t>(Bits);
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uint64_t Operand = Upper26 | Lower6;
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return Operand;
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}
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static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
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return *static_cast<HexagonDisassembler const *>(Decoder);
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}
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template <size_t T>
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static void signedDecoder(MCInst &MI, unsigned tmp,
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const MCDisassembler *Decoder) {
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HexagonDisassembler const &Disassembler = disassembler(Decoder);
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int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
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int64_t Extended = SignExtend64<32>(FullValue);
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HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
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}
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}
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// Forward declare these because the auto-generated code will reference them.
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// Definitions are further down.
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus
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DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t Address,
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const MCDisassembler *Decoder);
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static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/,
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const MCDisassembler *Decoder);
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static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const MCDisassembler *Decoder);
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#include "HexagonDepDecoders.inc"
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#include "HexagonGenDisassemblerTables.inc"
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static MCDisassembler *createHexagonDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler() {
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TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
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createHexagonDisassembler);
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}
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DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &cs) const {
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DecodeStatus Result = DecodeStatus::Success;
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bool Complete = false;
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Size = 0;
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*CurrentBundle = &MI;
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MI.setOpcode(Hexagon::BUNDLE);
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MI.addOperand(MCOperand::createImm(0));
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while (Result == Success && !Complete) {
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if (Bytes.size() < HEXAGON_INSTR_SIZE)
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return MCDisassembler::Fail;
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MCInst *Inst = getContext().createMCInst();
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Result = getSingleInstruction(*Inst, MI, Bytes, Address, cs, Complete);
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MI.addOperand(MCOperand::createInst(Inst));
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Size += HEXAGON_INSTR_SIZE;
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Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
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}
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if (Result == MCDisassembler::Fail)
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return Result;
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if (Size > HEXAGON_MAX_PACKET_SIZE)
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return MCDisassembler::Fail;
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const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
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const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
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HexagonMCChecker Checker(getContext(), *MCII, STI_, MI,
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*getContext().getRegisterInfo(), false);
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if (!Checker.check())
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return MCDisassembler::Fail;
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remapInstruction(MI);
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return MCDisassembler::Success;
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}
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void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
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for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
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auto &MI = const_cast<MCInst &>(*I.getInst());
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switch (MI.getOpcode()) {
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case Hexagon::S2_allocframe:
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if (MI.getOperand(0).getReg() == Hexagon::R29) {
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MI.setOpcode(Hexagon::S6_allocframe_to_raw);
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MI.erase(MI.begin () + 1);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L2_deallocframe:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(1).getReg() == Hexagon::R30) {
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MI.setOpcode(L6_deallocframe_map_to_raw);
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MI.erase(MI.begin () + 1);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(1).getReg() == Hexagon::R30) {
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MI.setOpcode(L6_return_map_to_raw);
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MI.erase(MI.begin () + 1);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_t:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_t);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_f:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_f);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_tnew_pt:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_tnew_pt);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_fnew_pt:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_fnew_pt);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_tnew_pnt:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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case Hexagon::L4_return_fnew_pnt:
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if (MI.getOperand(0).getReg() == Hexagon::D15 &&
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MI.getOperand(2).getReg() == Hexagon::R30) {
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MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
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MI.erase(MI.begin () + 2);
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MI.erase(MI.begin ());
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}
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break;
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}
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}
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}
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static void adjustDuplex(MCInst &MI, MCContext &Context) {
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switch (MI.getOpcode()) {
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case Hexagon::SA1_setin1:
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MI.insert(MI.begin() + 1,
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MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
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break;
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case Hexagon::SA1_dec:
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MI.insert(MI.begin() + 2,
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MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
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break;
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default:
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break;
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}
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}
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DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &cs,
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bool &Complete) const {
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assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
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uint32_t Instruction = support::endian::read32le(Bytes.data());
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auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_LOOP_END) {
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if (BundleSize == 0)
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HexagonMCInstrInfo::setInnerLoop(MCB);
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else if (BundleSize == 1)
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HexagonMCInstrInfo::setOuterLoop(MCB);
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else
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return DecodeStatus::Fail;
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}
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CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
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MCB, HexagonMCInstrInfo::bundleSize(MCB));
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DecodeStatus Result = DecodeStatus::Fail;
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_DUPLEX) {
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unsigned duplexIClass;
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uint8_t const *DecodeLow, *DecodeHigh;
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duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
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switch (duplexIClass) {
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default:
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return MCDisassembler::Fail;
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case 0:
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DecodeLow = DecoderTableSUBINSN_L132;
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DecodeHigh = DecoderTableSUBINSN_L132;
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break;
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case 1:
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DecodeLow = DecoderTableSUBINSN_L232;
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DecodeHigh = DecoderTableSUBINSN_L132;
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break;
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case 2:
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DecodeLow = DecoderTableSUBINSN_L232;
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DecodeHigh = DecoderTableSUBINSN_L232;
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break;
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case 3:
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DecodeLow = DecoderTableSUBINSN_A32;
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DecodeHigh = DecoderTableSUBINSN_A32;
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break;
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case 4:
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DecodeLow = DecoderTableSUBINSN_L132;
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DecodeHigh = DecoderTableSUBINSN_A32;
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break;
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case 5:
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DecodeLow = DecoderTableSUBINSN_L232;
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DecodeHigh = DecoderTableSUBINSN_A32;
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break;
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case 6:
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DecodeLow = DecoderTableSUBINSN_S132;
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DecodeHigh = DecoderTableSUBINSN_A32;
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break;
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case 7:
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DecodeLow = DecoderTableSUBINSN_S232;
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DecodeHigh = DecoderTableSUBINSN_A32;
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break;
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case 8:
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DecodeLow = DecoderTableSUBINSN_S132;
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DecodeHigh = DecoderTableSUBINSN_L132;
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break;
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case 9:
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DecodeLow = DecoderTableSUBINSN_S132;
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DecodeHigh = DecoderTableSUBINSN_L232;
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break;
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case 10:
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DecodeLow = DecoderTableSUBINSN_S132;
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DecodeHigh = DecoderTableSUBINSN_S132;
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break;
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case 11:
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DecodeLow = DecoderTableSUBINSN_S232;
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DecodeHigh = DecoderTableSUBINSN_S132;
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break;
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case 12:
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DecodeLow = DecoderTableSUBINSN_S232;
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DecodeHigh = DecoderTableSUBINSN_L132;
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break;
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case 13:
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DecodeLow = DecoderTableSUBINSN_S232;
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DecodeHigh = DecoderTableSUBINSN_L232;
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break;
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case 14:
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DecodeLow = DecoderTableSUBINSN_S232;
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DecodeHigh = DecoderTableSUBINSN_S232;
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break;
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}
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MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
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MCInst *MILow = getContext().createMCInst();
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MCInst *MIHigh = getContext().createMCInst();
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auto TmpExtender = CurrentExtender;
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CurrentExtender =
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nullptr; // constant extenders in duplex must always be in slot 1
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Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
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this, STI);
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CurrentExtender = TmpExtender;
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if (Result != DecodeStatus::Success)
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return DecodeStatus::Fail;
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adjustDuplex(*MILow, getContext());
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Result = decodeInstruction(
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DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
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if (Result != DecodeStatus::Success)
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return DecodeStatus::Fail;
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adjustDuplex(*MIHigh, getContext());
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MCOperand OPLow = MCOperand::createInst(MILow);
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MCOperand OPHigh = MCOperand::createInst(MIHigh);
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MI.addOperand(OPLow);
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MI.addOperand(OPHigh);
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Complete = true;
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} else {
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_PACKET_END)
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Complete = true;
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if (CurrentExtender != nullptr)
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Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
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Address, this, STI);
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if (Result != MCDisassembler::Success)
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Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
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STI);
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if (Result != MCDisassembler::Success &&
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STI.getFeatureBits()[Hexagon::ExtensionHVX])
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Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
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Address, this, STI);
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}
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switch (MI.getOpcode()) {
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case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
|
|
case Hexagon::J4_cmpeqn1_f_jumpnv_t:
|
|
case Hexagon::J4_cmpeqn1_fp0_jump_nt:
|
|
case Hexagon::J4_cmpeqn1_fp0_jump_t:
|
|
case Hexagon::J4_cmpeqn1_fp1_jump_nt:
|
|
case Hexagon::J4_cmpeqn1_fp1_jump_t:
|
|
case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
|
|
case Hexagon::J4_cmpeqn1_t_jumpnv_t:
|
|
case Hexagon::J4_cmpeqn1_tp0_jump_nt:
|
|
case Hexagon::J4_cmpeqn1_tp0_jump_t:
|
|
case Hexagon::J4_cmpeqn1_tp1_jump_nt:
|
|
case Hexagon::J4_cmpeqn1_tp1_jump_t:
|
|
case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
|
|
case Hexagon::J4_cmpgtn1_f_jumpnv_t:
|
|
case Hexagon::J4_cmpgtn1_fp0_jump_nt:
|
|
case Hexagon::J4_cmpgtn1_fp0_jump_t:
|
|
case Hexagon::J4_cmpgtn1_fp1_jump_nt:
|
|
case Hexagon::J4_cmpgtn1_fp1_jump_t:
|
|
case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
|
|
case Hexagon::J4_cmpgtn1_t_jumpnv_t:
|
|
case Hexagon::J4_cmpgtn1_tp0_jump_nt:
|
|
case Hexagon::J4_cmpgtn1_tp0_jump_t:
|
|
case Hexagon::J4_cmpgtn1_tp1_jump_nt:
|
|
case Hexagon::J4_cmpgtn1_tp1_jump_t:
|
|
MI.insert(MI.begin() + 1,
|
|
MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
|
|
unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
|
|
MCOperand &MCO = MI.getOperand(OpIndex);
|
|
assert(MCO.isReg() && "New value consumers must be registers");
|
|
unsigned Register =
|
|
getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
|
|
if ((Register & 0x6) == 0)
|
|
// HexagonPRM 10.11 Bit 1-2 == 0 is reserved
|
|
return MCDisassembler::Fail;
|
|
unsigned Lookback = (Register & 0x6) >> 1;
|
|
unsigned Offset = 1;
|
|
bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
|
|
bool PrevVector = false;
|
|
auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
|
|
auto i = Instructions.end() - 1;
|
|
for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
|
|
if (i == n)
|
|
// Couldn't find producer
|
|
return MCDisassembler::Fail;
|
|
bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
|
|
if (Vector && !CurrentVector)
|
|
// Skip scalars when calculating distances for vectors
|
|
++Lookback;
|
|
if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
|
|
++Lookback;
|
|
PrevVector = CurrentVector;
|
|
if (Offset == Lookback)
|
|
break;
|
|
}
|
|
auto const &Inst = *i->getInst();
|
|
bool SubregBit = (Register & 0x1) != 0;
|
|
if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
|
|
// If subreg bit is set we're selecting the second produced newvalue
|
|
unsigned Producer = SubregBit ?
|
|
HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
|
|
HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
|
|
assert(Producer != Hexagon::NoRegister);
|
|
MCO.setReg(Producer);
|
|
} else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
|
|
unsigned Producer =
|
|
HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
|
|
|
|
if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
|
|
const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
|
|
const unsigned ProdPairIndex =
|
|
Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
|
|
Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
|
|
} else if (SubregBit)
|
|
// Hexagon PRM 10.11 New-value operands
|
|
// Nt[0] is reserved and should always be encoded as zero.
|
|
return MCDisassembler::Fail;
|
|
assert(Producer != Hexagon::NoRegister);
|
|
MCO.setReg(Producer);
|
|
} else
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
if (CurrentExtender != nullptr) {
|
|
MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
|
|
? *MI.getOperand(1).getInst()
|
|
: MI;
|
|
if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
|
|
!HexagonMCInstrInfo::isExtended(*MCII, Inst))
|
|
return MCDisassembler::Fail;
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
ArrayRef<MCPhysReg> Table) {
|
|
if (RegNo < Table.size()) {
|
|
Inst.addOperand(MCOperand::createReg(Table[RegNo]));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
|
|
}
|
|
|
|
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg IntRegDecoderTable[] = {
|
|
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
|
|
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
|
|
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
|
|
Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
|
|
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
|
|
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
|
|
Hexagon::R30, Hexagon::R31};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg GeneralSubRegDecoderTable[] = {
|
|
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
|
|
Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
|
|
Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
|
|
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
|
|
};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg HvxVRDecoderTable[] = {
|
|
Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
|
|
Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
|
|
Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
|
|
Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
|
|
Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
|
|
Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
|
|
Hexagon::V30, Hexagon::V31};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg DoubleRegDecoderTable[] = {
|
|
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
|
|
Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
|
|
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
|
|
Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
|
|
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
|
|
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg HvxWRDecoderTable[] = {
|
|
Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
|
|
Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
|
|
Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
|
|
Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
|
|
Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
|
|
Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
|
|
Hexagon::W15, Hexagon::WR15,
|
|
};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
|
|
}
|
|
|
|
LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily.
|
|
static DecodeStatus
|
|
DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg HvxVQRDecoderTable[] = {
|
|
Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
|
|
Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
|
|
Hexagon::P2, Hexagon::P3};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
|
|
Hexagon::Q2, Hexagon::Q3};
|
|
|
|
return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
|
|
}
|
|
|
|
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
using namespace Hexagon;
|
|
|
|
static const MCPhysReg CtrlRegDecoderTable[] = {
|
|
/* 0 */ SA0, LC0, SA1, LC1,
|
|
/* 4 */ P3_0, C5, M0, M1,
|
|
/* 8 */ USR, PC, UGP, GP,
|
|
/* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
|
|
/* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
|
|
/* 20 */ 0, 0, 0, 0,
|
|
/* 24 */ 0, 0, 0, 0,
|
|
/* 28 */ 0, 0, UTIMERLO, UTIMERHI
|
|
};
|
|
|
|
if (RegNo >= array_lengthof(CtrlRegDecoderTable))
|
|
return MCDisassembler::Fail;
|
|
|
|
static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
|
|
if (CtrlRegDecoderTable[RegNo] == NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = CtrlRegDecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
using namespace Hexagon;
|
|
|
|
static const MCPhysReg CtrlReg64DecoderTable[] = {
|
|
/* 0 */ C1_0, 0, C3_2, 0,
|
|
/* 4 */ C5_4, 0, C7_6, 0,
|
|
/* 8 */ C9_8, 0, C11_10, 0,
|
|
/* 12 */ CS, 0, UPCYCLE, 0,
|
|
/* 16 */ C17_16, 0, PKTCOUNT, 0,
|
|
/* 20 */ 0, 0, 0, 0,
|
|
/* 24 */ 0, 0, 0, 0,
|
|
/* 28 */ 0, 0, UTIMER, 0
|
|
};
|
|
|
|
if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
|
|
return MCDisassembler::Fail;
|
|
|
|
static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
|
|
if (CtrlReg64DecoderTable[RegNo] == NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = CtrlReg64DecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
unsigned Register = 0;
|
|
switch (RegNo) {
|
|
case 0:
|
|
Register = Hexagon::M0;
|
|
break;
|
|
case 1:
|
|
Register = Hexagon::M1;
|
|
break;
|
|
default:
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
HexagonDisassembler const &Disassembler = disassembler(Decoder);
|
|
int64_t FullValue = fullValue(Disassembler, MI, tmp);
|
|
assert(FullValue >= 0 && "Negative in unsigned decoder");
|
|
HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
HexagonDisassembler const &Disassembler = disassembler(Decoder);
|
|
unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
|
|
tmp = SignExtend64(tmp, Bits);
|
|
signedDecoder<32>(MI, tmp, Decoder);
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
// custom decoder for various jump/call immediates
|
|
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
HexagonDisassembler const &Disassembler = disassembler(Decoder);
|
|
unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
|
|
// r13_2 is not extendable, so if there are no extent bits, it's r13_2
|
|
if (Bits == 0)
|
|
Bits = 15;
|
|
uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
|
|
uint32_t Extended = FullValue + Address;
|
|
if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
|
|
4))
|
|
HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static const uint16_t SysRegDecoderTable[] = {
|
|
Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
|
|
Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
|
|
Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
|
|
Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
|
|
Hexagon::S12, Hexagon::S13, Hexagon::S14,
|
|
Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
|
|
Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
|
|
Hexagon::VID, Hexagon::S22, Hexagon::S23,
|
|
Hexagon::S24, Hexagon::S25, Hexagon::S26,
|
|
Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
|
|
Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
|
|
Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
|
|
Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
|
|
Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
|
|
Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
|
|
Hexagon::S45, Hexagon::S46, Hexagon::S47,
|
|
Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
|
|
Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
|
|
Hexagon::S54, Hexagon::S55, Hexagon::S56,
|
|
Hexagon::S57, Hexagon::S58, Hexagon::S59,
|
|
Hexagon::S60, Hexagon::S61, Hexagon::S62,
|
|
Hexagon::S63, Hexagon::S64, Hexagon::S65,
|
|
Hexagon::S66, Hexagon::S67, Hexagon::S68,
|
|
Hexagon::S69, Hexagon::S70, Hexagon::S71,
|
|
Hexagon::S72, Hexagon::S73, Hexagon::S74,
|
|
Hexagon::S75, Hexagon::S76, Hexagon::S77,
|
|
Hexagon::S78, Hexagon::S79, Hexagon::S80,
|
|
};
|
|
|
|
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0]))
|
|
return MCDisassembler::Fail;
|
|
|
|
if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = SysRegDecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static const uint16_t SysReg64DecoderTable[] = {
|
|
Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
|
|
Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
|
|
Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
|
|
Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
|
|
Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
|
|
Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
|
|
Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
|
|
Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
|
|
Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
|
|
Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
|
|
};
|
|
|
|
static DecodeStatus
|
|
DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
RegNo = RegNo >> 1;
|
|
if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0]))
|
|
return MCDisassembler::Fail;
|
|
|
|
if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = SysReg64DecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
using namespace Hexagon;
|
|
|
|
static const MCPhysReg GuestRegDecoderTable[] = {
|
|
/* 0 */ GELR, GSR, GOSP, G3,
|
|
/* 4 */ G4, G5, G6, G7,
|
|
/* 8 */ G8, G9, G10, G11,
|
|
/* 12 */ G12, G13, G14, G15,
|
|
/* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
|
|
/* 20 */ G20, G21, G22, G23,
|
|
/* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
|
|
/* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
|
|
};
|
|
|
|
if (RegNo >= array_lengthof(GuestRegDecoderTable))
|
|
return MCDisassembler::Fail;
|
|
if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = GuestRegDecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus
|
|
DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
|
|
uint64_t /*Address*/,
|
|
const MCDisassembler *Decoder) {
|
|
using namespace Hexagon;
|
|
|
|
static const MCPhysReg GuestReg64DecoderTable[] = {
|
|
/* 0 */ G1_0, 0, G3_2, 0,
|
|
/* 4 */ G5_4, 0, G7_6, 0,
|
|
/* 8 */ G9_8, 0, G11_10, 0,
|
|
/* 12 */ G13_12, 0, G15_14, 0,
|
|
/* 16 */ G17_16, 0, G19_18, 0,
|
|
/* 20 */ G21_20, 0, G23_22, 0,
|
|
/* 24 */ G25_24, 0, G27_26, 0,
|
|
/* 28 */ G29_28, 0, G31_30, 0
|
|
};
|
|
|
|
if (RegNo >= array_lengthof(GuestReg64DecoderTable))
|
|
return MCDisassembler::Fail;
|
|
if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
|
|
return MCDisassembler::Fail;
|
|
|
|
unsigned Register = GuestReg64DecoderTable[RegNo];
|
|
Inst.addOperand(MCOperand::createReg(Register));
|
|
return MCDisassembler::Success;
|
|
}
|