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llvm-project/llvm/lib/Target/RISCV
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Yeting Kuo f68cad9087 [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs. 
The patch is a replacement of D125199. PseudoReadVL with vtype has worry for
computing same vtypes of VLEFF/VLSEGFF in two different places, DAGToDAG and
InsertVSETVLI. VLEFF/VLSEGFF MI with VL output still could provide the vtype of
VLEFF/VLSEGFF to the users of its VL.

The patch names the new pseudo as original VLEFF/VLSEGFF name suffixed "_VL" and
expand them in RISCVInsertVSETVLI pass.

This patch also reverts commit 4537aae0d57e17c217c192d8977012ba475b130c,
"[RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.".

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126794
2022-06-10 13:57:10 +08:00
..
AsmParser
[MC] Change EndOfStatement "unexpected tokens in .xxx directive " to "expected newline"
2022-06-05 15:11:01 -07:00
Disassembler
Rename MCFixedLenDisassembler.h as MCDecoderOps.h
2022-05-15 08:44:58 +08:00
MCTargetDesc
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
RISCV.h
[RISCV] Pass OptLevel to RISCVDAGToDAGISel correctly
2022-05-30 17:22:50 -07:00
RISCV.td
[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
2022-05-26 15:25:47 -07:00
RISCVAsmPrinter.cpp
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
[RISCV] Fix missing stack pointer recover
2022-06-09 23:38:50 +08:00
RISCVFrameLowering.h
[RISCV] Fix RVV stack frame alignment bugs
2022-05-24 06:53:51 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Add caching to the gather/scatter to strided load/store conversion.
2022-05-11 11:47:27 -07:00
RISCVInsertVSETVLI.cpp
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
RISCVInstrInfo.h
[RISCV] Enable MachineOutliner by default under -Oz for RISCV
2022-05-06 17:37:45 +08:00
RISCVInstrInfo.td
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVInstrInfoA.td
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVInstrInfoC.td
[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoF.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoM.td
[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
2022-04-25 10:53:41 -07:00
RISCVInstrInfoV.td
[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
2022-03-31 01:33:17 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Replace ISD::FP_EXTEND and ISD::FP_ROUND with RVV VL op.
2022-05-26 02:17:31 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL.
2022-05-24 21:38:59 -07:00
RISCVInstrInfoZb.td
[RISCV] Give CSImm12MulBy4 PatLeaf priority over CSImm12MulBy8. NFC
2022-06-02 20:51:14 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
RISCVISelDAGToDAG.h
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVISelLowering.cpp
[RISCV] Add ISD::EH_DWARF_CFA
2022-06-08 22:03:30 +08:00
RISCVISelLowering.h
[RISCV] Add ISD::EH_DWARF_CFA
2022-06-08 22:03:30 +08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMachineFunctionInfo.h
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMakeCompressible.cpp
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
RISCVMCInstLower.cpp
[RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.
2022-06-10 13:57:10 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates.
2022-06-09 16:07:35 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
Teach PeepholeOpt to eliminate redundant copy from constant physreg (e.g VLENB on RISCV)
2022-05-16 16:38:30 -07:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSExtWRemoval.cpp
[RISCV] transform MI to W variant to remove sext.w
2022-04-22 10:59:26 -07:00
RISCVSubtarget.cpp
Revert "[RISCV] Enable subregister liveness tracking for RVV."
2022-05-13 10:59:58 -07:00
RISCVSubtarget.h
[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
2022-05-26 15:25:47 -07:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
[RISCV] Pass OptLevel to RISCVDAGToDAGISel correctly
2022-05-30 17:22:50 -07:00
RISCVTargetMachine.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add cost model for reverse shuffle
2022-06-09 07:21:40 -07:00
RISCVTargetTransformInfo.h
[RISCV] Scalarize gather/scatter on RV64 with Zve32* extension.
2022-06-07 08:07:50 -07:00