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llvm-project/llvm/test/CodeGen/AArch64/extract-lowbits.ll
David Green adec922361 [AArch64] Make -mcpu=generic schedule for an in-order core 
We would like to start pushing -mcpu=generic towards enabling the set of
features that improves performance for some CPUs, without hurting any
others. A blend of the performance options hopefully beneficial to all
CPUs. The largest part of that is enabling in-order scheduling using the
Cortex-A55 schedule model. This is similar to the Arm backend change
from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling
using the cortex-a8 schedule model.

The idea is that in-order cpu's require the most help in instruction
scheduling, whereas out-of-order cpus can for the most part out-of-order
schedule around different codegen. Our benchmarking suggests that
hypothesis holds. When running on an in-order core this improved
performance by 3.8% geomean on a set of DSP workloads, 2% geomean on
some other embedded benchmark and between 1% and 1.8% on a set of
singlecore and multicore workloads, all running on a Cortex-A55 cluster.

On an out-of-order cpu the results are a lot more noisy but show flat
performance or an improvement. On the set of DSP and embedded
benchmarks, run on a Cortex-A78 there was a very noisy 1% speed
improvement. Using the most detailed results I could find, SPEC2006 runs
on a Neoverse N1 show a small increase in instruction count (+0.127%),
but a decrease in cycle counts (-0.155%, on average). The instruction
count is very low noise, the cycle count is more noisy with a 0.15%
decrease not being significant. SPEC2k17 shows a small decrease (-0.2%)
in instruction count leading to a -0.296% decrease in cycle count. These
results are within noise margins but tend to show a small improvement in
general.

When specifying an Apple target, clang will set "-target-cpu apple-a7"
on the command line, so should not be affected by this change when
running from clang. This also doesn't enable more runtime unrolling like
-mcpu=cortex-a55 does, only changing the schedule used.

A lot of existing tests have updated. This is a summary of the important
differences:
 - Most changes are the same instructions in a different order.
 - Sometimes this leads to very minor inefficiencies, such as requiring
   an extra mov to move variables into r0/v0 for the return value of a test
   function.
 - misched-fusion.ll was no longer fusing the pairs of instructions it
   should, as per D110561. I've changed the schedule used in the test
   for now.
 - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to
   the different latencies. This seems fine to me.
 - Some SVE tests do not always remove movprfx where they did before due
   to different register allocation giving different destructive forms.
 - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll
   produce two LDR where they previously produced an LDP due to
   store-pair-suppress kicking in.
 - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD.
 - Some tests such as arm64-neon-mul-div.ll and
   ragreedy-local-interval-cost.ll have more, less or just different
   spilling.
 - In aarch64_generated_funcs.ll.generated.expected one part of the
   function is no longer outlined. Interestingly if I switch this to use
   any other scheduled even less is outlined.

Some of these are expected to happen, such as differences in outlining
or register spilling. There will be places where these result in worse
codegen, places where they are better, with the SPEC instruction counts
suggesting it is not a decrease overall, on average.

Differential Revision: https://reviews.llvm.org/D110830
2021-10-09 15:58:31 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
; *Please* keep in sync with test/CodeGen/X86/extract-lowbits.ll
; https://bugs.llvm.org/show_bug.cgi?id=36419
; https://bugs.llvm.org/show_bug.cgi?id=37603
; https://bugs.llvm.org/show_bug.cgi?id=37610
; Patterns:
; a) x & (1 << nbits) - 1
; b) x & ~(-1 << nbits)
; c) x & (-1 >> (32 - y))
; d) x << (32 - y) >> (32 - y)
; are equivalent.
; ---------------------------------------------------------------------------- ;
; Pattern a. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_a2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_a3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%conv = zext i8 %numlowbits to i32
%onebit = shl i32 1, %conv
%mask = add nsw i32 %onebit, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: sub w8, w8, #1
; CHECK-NEXT: and w0, w0, w8
; CHECK-NEXT: ret
%onebit = shl i32 1, %numlowbits
%mask = add nsw i32 %onebit, -1
%masked = and i32 %val, %mask ; swapped order
ret i32 %masked
}
; 64-bit
define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a0:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_a2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_a3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%conv = zext i8 %numlowbits to i64
%onebit = shl i64 1, %conv
%mask = add nsw i64 %onebit, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_a4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: and x0, x0, x8
; CHECK-NEXT: ret
%onebit = shl i64 1, %numlowbits
%mask = add nsw i64 %onebit, -1
%masked = and i64 %val, %mask ; swapped order
ret i64 %masked
}
; ---------------------------------------------------------------------------- ;
; Pattern b. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bzhi32_b0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_b0:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: bic w0, w0, w8
; CHECK-NEXT: ret
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_b1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: bic w0, w0, w8
; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i32
%notmask = shl i32 -1, %conv
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_b2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_b2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: bic w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_b3_load_indexzext(i32* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_b3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: lsl w9, w9, w1
; CHECK-NEXT: bic w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%conv = zext i8 %numlowbits to i32
%notmask = shl i32 -1, %conv
%mask = xor i32 %notmask, -1
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_b4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1
; CHECK-NEXT: lsl w8, w8, w1
; CHECK-NEXT: bic w0, w0, w8
; CHECK-NEXT: ret
%notmask = shl i32 -1, %numlowbits
%mask = xor i32 %notmask, -1
%masked = and i32 %val, %mask ; swapped order
ret i32 %masked
}
; 64-bit
define i64 @bzhi64_b0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_b0:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: bic x0, x0, x8
; CHECK-NEXT: ret
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_b1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_b1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: bic x0, x0, x8
; CHECK-NEXT: ret
%conv = zext i8 %numlowbits to i64
%notmask = shl i64 -1, %conv
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_b2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_b2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: bic x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_b3_load_indexzext(i64* %w, i8 zeroext %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_b3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
; CHECK-NEXT: lsl x9, x9, x1
; CHECK-NEXT: bic x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%conv = zext i8 %numlowbits to i64
%notmask = shl i64 -1, %conv
%mask = xor i64 %notmask, -1
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_b4_commutative(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_b4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #-1
; CHECK-NEXT: lsl x8, x8, x1
; CHECK-NEXT: bic x0, x0, x8
; CHECK-NEXT: ret
%notmask = shl i64 -1, %numlowbits
%mask = xor i64 %notmask, -1
%masked = and i64 %val, %mask ; swapped order
ret i64 %masked
}
; ---------------------------------------------------------------------------- ;
; Pattern c. 32-bit
; ---------------------------------------------------------------------------- ;
define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c0:
; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: lsr w8, w9, w8
; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsr w8, w9, w8
; CHECK-NEXT: and w0, w8, w0
; CHECK-NEXT: ret
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%mask = lshr i32 -1, %sh_prom
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_c2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: mov w10, #-1
; CHECK-NEXT: lsr w8, w10, w8
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_c3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: mov w10, #-1
; CHECK-NEXT: lsr w8, w10, w8
; CHECK-NEXT: and w0, w8, w9
; CHECK-NEXT: ret
%val = load i32, i32* %w
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%mask = lshr i32 -1, %sh_prom
%masked = and i32 %mask, %val
ret i32 %masked
}
define i32 @bzhi32_c4_commutative(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_c4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: mov w9, #-1
; CHECK-NEXT: lsr w8, w9, w8
; CHECK-NEXT: and w0, w0, w8
; CHECK-NEXT: ret
%numhighbits = sub i32 32, %numlowbits
%mask = lshr i32 -1, %numhighbits
%masked = and i32 %val, %mask ; swapped order
ret i32 %masked
}
; 64-bit
define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c0:
; CHECK: // %bb.0:
; CHECK-NEXT: neg x8, x1
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: lsr x8, x9, x8
; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsr x8, x9, x8
; CHECK-NEXT: and x0, x8, x0
; CHECK-NEXT: ret
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%mask = lshr i64 -1, %sh_prom
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_c2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: neg x8, x1
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: mov x10, #-1
; CHECK-NEXT: lsr x8, x10, x8
; CHECK-NEXT: and x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_c3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: mov x10, #-1
; CHECK-NEXT: lsr x8, x10, x8
; CHECK-NEXT: and x0, x8, x9
; CHECK-NEXT: ret
%val = load i64, i64* %w
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%mask = lshr i64 -1, %sh_prom
%masked = and i64 %mask, %val
ret i64 %masked
}
define i64 @bzhi64_c4_commutative(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_c4_commutative:
; CHECK: // %bb.0:
; CHECK-NEXT: neg x8, x1
; CHECK-NEXT: mov x9, #-1
; CHECK-NEXT: lsr x8, x9, x8
; CHECK-NEXT: and x0, x0, x8
; CHECK-NEXT: ret
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits
%masked = and i64 %val, %mask ; swapped order
ret i64 %masked
}
; ---------------------------------------------------------------------------- ;
; Pattern d. 32-bit.
; ---------------------------------------------------------------------------- ;
define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d0:
; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: lsl w9, w0, w8
; CHECK-NEXT: lsr w0, w9, w8
; CHECK-NEXT: ret
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %val, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
ret i32 %masked
}
define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl w9, w0, w8
; CHECK-NEXT: lsr w0, w9, w8
; CHECK-NEXT: ret
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%highbitscleared = shl i32 %val, %sh_prom
%masked = lshr i32 %highbitscleared, %sh_prom
ret i32 %masked
}
define i32 @bzhi32_d2_load(i32* %w, i32 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w1
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: lsl w9, w9, w8
; CHECK-NEXT: lsr w0, w9, w8
; CHECK-NEXT: ret
%val = load i32, i32* %w
%numhighbits = sub i32 32, %numlowbits
%highbitscleared = shl i32 %val, %numhighbits
%masked = lshr i32 %highbitscleared, %numhighbits
ret i32 %masked
}
define i32 @bzhi32_d3_load_indexzext(i32* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi32_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32
; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl w9, w9, w8
; CHECK-NEXT: lsr w0, w9, w8
; CHECK-NEXT: ret
%val = load i32, i32* %w
%numhighbits = sub i8 32, %numlowbits
%sh_prom = zext i8 %numhighbits to i32
%highbitscleared = shl i32 %val, %sh_prom
%masked = lshr i32 %highbitscleared, %sh_prom
ret i32 %masked
}
; 64-bit.
define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d0:
; CHECK: // %bb.0:
; CHECK-NEXT: neg x8, x1
; CHECK-NEXT: lsl x9, x0, x8
; CHECK-NEXT: lsr x0, x9, x8
; CHECK-NEXT: ret
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %val, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
ret i64 %masked
}
define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d1_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl x9, x0, x8
; CHECK-NEXT: lsr x0, x9, x8
; CHECK-NEXT: ret
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%highbitscleared = shl i64 %val, %sh_prom
%masked = lshr i64 %highbitscleared, %sh_prom
ret i64 %masked
}
define i64 @bzhi64_d2_load(i64* %w, i64 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d2_load:
; CHECK: // %bb.0:
; CHECK-NEXT: neg x8, x1
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: lsl x9, x9, x8
; CHECK-NEXT: lsr x0, x9, x8
; CHECK-NEXT: ret
%val = load i64, i64* %w
%numhighbits = sub i64 64, %numlowbits
%highbitscleared = shl i64 %val, %numhighbits
%masked = lshr i64 %highbitscleared, %numhighbits
ret i64 %masked
}
define i64 @bzhi64_d3_load_indexzext(i64* %w, i8 %numlowbits) nounwind {
; CHECK-LABEL: bzhi64_d3_load_indexzext:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #64
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: sub w8, w8, w1
; CHECK-NEXT: lsl x9, x9, x8
; CHECK-NEXT: lsr x0, x9, x8
; CHECK-NEXT: ret
%val = load i64, i64* %w
%numhighbits = sub i8 64, %numlowbits
%sh_prom = zext i8 %numhighbits to i64
%highbitscleared = shl i64 %val, %sh_prom
%masked = lshr i64 %highbitscleared, %sh_prom
ret i64 %masked
}
; ---------------------------------------------------------------------------- ;
; Constant mask
; ---------------------------------------------------------------------------- ;
; 32-bit
define i32 @bzhi32_constant_mask32(i32 %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x7fffffff
; CHECK-NEXT: ret
%masked = and i32 %val, 2147483647
ret i32 %masked
}
define i32 @bzhi32_constant_mask32_load(i32* %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask32_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: and w0, w8, #0x7fffffff
; CHECK-NEXT: ret
%val1 = load i32, i32* %val
%masked = and i32 %val1, 2147483647
ret i32 %masked
}
define i32 @bzhi32_constant_mask16(i32 %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x7fff
; CHECK-NEXT: ret
%masked = and i32 %val, 32767
ret i32 %masked
}
define i32 @bzhi32_constant_mask16_load(i32* %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask16_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: and w0, w8, #0x7fff
; CHECK-NEXT: ret
%val1 = load i32, i32* %val
%masked = and i32 %val1, 32767
ret i32 %masked
}
define i32 @bzhi32_constant_mask8(i32 %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, #0x7f
; CHECK-NEXT: ret
%masked = and i32 %val, 127
ret i32 %masked
}
define i32 @bzhi32_constant_mask8_load(i32* %val) nounwind {
; CHECK-LABEL: bzhi32_constant_mask8_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr w8, [x0]
; CHECK-NEXT: and w0, w8, #0x7f
; CHECK-NEXT: ret
%val1 = load i32, i32* %val
%masked = and i32 %val1, 127
ret i32 %masked
}
; 64-bit
define i64 @bzhi64_constant_mask64(i64 %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask64:
; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, #0x3fffffffffffffff
; CHECK-NEXT: ret
%masked = and i64 %val, 4611686018427387903
ret i64 %masked
}
define i64 @bzhi64_constant_mask64_load(i64* %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask64_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: and x0, x8, #0x3fffffffffffffff
; CHECK-NEXT: ret
%val1 = load i64, i64* %val
%masked = and i64 %val1, 4611686018427387903
ret i64 %masked
}
define i64 @bzhi64_constant_mask32(i64 %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask32:
; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, #0x7fffffff
; CHECK-NEXT: ret
%masked = and i64 %val, 2147483647
ret i64 %masked
}
define i64 @bzhi64_constant_mask32_load(i64* %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask32_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: and x0, x8, #0x7fffffff
; CHECK-NEXT: ret
%val1 = load i64, i64* %val
%masked = and i64 %val1, 2147483647
ret i64 %masked
}
define i64 @bzhi64_constant_mask16(i64 %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask16:
; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, #0x7fff
; CHECK-NEXT: ret
%masked = and i64 %val, 32767
ret i64 %masked
}
define i64 @bzhi64_constant_mask16_load(i64* %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask16_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: and x0, x8, #0x7fff
; CHECK-NEXT: ret
%val1 = load i64, i64* %val
%masked = and i64 %val1, 32767
ret i64 %masked
}
define i64 @bzhi64_constant_mask8(i64 %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask8:
; CHECK: // %bb.0:
; CHECK-NEXT: and x0, x0, #0x7f
; CHECK-NEXT: ret
%masked = and i64 %val, 127
ret i64 %masked
}
define i64 @bzhi64_constant_mask8_load(i64* %val) nounwind {
; CHECK-LABEL: bzhi64_constant_mask8_load:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: and x0, x8, #0x7f
; CHECK-NEXT: ret
%val1 = load i64, i64* %val
%masked = and i64 %val1, 127
ret i64 %masked
}
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