adec922361
We would like to start pushing -mcpu=generic towards enabling the set of features that improves performance for some CPUs, without hurting any others. A blend of the performance options hopefully beneficial to all CPUs. The largest part of that is enabling in-order scheduling using the Cortex-A55 schedule model. This is similar to the Arm backend change from eecb353d0e25ba which made -mcpu=generic perform in-order scheduling using the cortex-a8 schedule model. The idea is that in-order cpu's require the most help in instruction scheduling, whereas out-of-order cpus can for the most part out-of-order schedule around different codegen. Our benchmarking suggests that hypothesis holds. When running on an in-order core this improved performance by 3.8% geomean on a set of DSP workloads, 2% geomean on some other embedded benchmark and between 1% and 1.8% on a set of singlecore and multicore workloads, all running on a Cortex-A55 cluster. On an out-of-order cpu the results are a lot more noisy but show flat performance or an improvement. On the set of DSP and embedded benchmarks, run on a Cortex-A78 there was a very noisy 1% speed improvement. Using the most detailed results I could find, SPEC2006 runs on a Neoverse N1 show a small increase in instruction count (+0.127%), but a decrease in cycle counts (-0.155%, on average). The instruction count is very low noise, the cycle count is more noisy with a 0.15% decrease not being significant. SPEC2k17 shows a small decrease (-0.2%) in instruction count leading to a -0.296% decrease in cycle count. These results are within noise margins but tend to show a small improvement in general. When specifying an Apple target, clang will set "-target-cpu apple-a7" on the command line, so should not be affected by this change when running from clang. This also doesn't enable more runtime unrolling like -mcpu=cortex-a55 does, only changing the schedule used. A lot of existing tests have updated. This is a summary of the important differences: - Most changes are the same instructions in a different order. - Sometimes this leads to very minor inefficiencies, such as requiring an extra mov to move variables into r0/v0 for the return value of a test function. - misched-fusion.ll was no longer fusing the pairs of instructions it should, as per D110561. I've changed the schedule used in the test for now. - neon-mla-mls.ll now uses "mul; sub" as opposed to "neg; mla" due to the different latencies. This seems fine to me. - Some SVE tests do not always remove movprfx where they did before due to different register allocation giving different destructive forms. - The tests argument-blocks-array-of-struct.ll and arm64-windows-calls.ll produce two LDR where they previously produced an LDP due to store-pair-suppress kicking in. - arm64-ldp.ll and arm64-neon-copy.ll are missing pre/postinc on LPD. - Some tests such as arm64-neon-mul-div.ll and ragreedy-local-interval-cost.ll have more, less or just different spilling. - In aarch64_generated_funcs.ll.generated.expected one part of the function is no longer outlined. Interestingly if I switch this to use any other scheduled even less is outlined. Some of these are expected to happen, such as differences in outlining or register spilling. There will be places where these result in worse codegen, places where they are better, with the SPEC instruction counts suggesting it is not a decrease overall, on average. Differential Revision: https://reviews.llvm.org/D110830
126 lines
3.3 KiB
LLVM
126 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define void @test_load_store(half* %in, half* %out) {
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; CHECK-LABEL: test_load_store:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: str h0, [x1]
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; CHECK-NEXT: ret
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%val = load half, half* %in
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store half %val, half* %out
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ret void
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}
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define i16 @test_bitcast_from_half(half* %addr) {
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; CHECK-LABEL: test_bitcast_from_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldrh w0, [x0]
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; CHECK-NEXT: ret
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%val = load half, half* %addr
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%val_int = bitcast half %val to i16
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ret i16 %val_int
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}
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define i16 @test_reg_bitcast_from_half(half %in) {
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; CHECK-LABEL: test_reg_bitcast_from_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $s0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%val = bitcast half %in to i16
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ret i16 %val
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}
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define void @test_bitcast_to_half(half* %addr, i16 %in) {
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; CHECK-LABEL: test_bitcast_to_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: strh w1, [x0]
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; CHECK-NEXT: ret
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%val_fp = bitcast i16 %in to half
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store half %val_fp, half* %addr
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ret void
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}
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define half @test_reg_bitcast_to_half(i16 %in) {
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; CHECK-LABEL: test_reg_bitcast_to_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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%val = bitcast i16 %in to half
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ret half %val
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}
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define float @test_extend32(half* %addr) {
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; CHECK-LABEL: test_extend32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: ret
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to float
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ret float %val32
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}
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define double @test_extend64(half* %addr) {
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; CHECK-LABEL: test_extend64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr h0, [x0]
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; CHECK-NEXT: fcvt d0, h0
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; CHECK-NEXT: ret
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%val16 = load half, half* %addr
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%val32 = fpext half %val16 to double
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ret double %val32
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}
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define void @test_trunc32(float %in, half* %addr) {
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; CHECK-LABEL: test_trunc32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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%val16 = fptrunc float %in to half
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store half %val16, half* %addr
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ret void
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}
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define void @test_trunc64(double %in, half* %addr) {
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; CHECK-LABEL: test_trunc64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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%val16 = fptrunc double %in to half
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store half %val16, half* %addr
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ret void
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}
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define i16 @test_fccmp(i1 %a, i16 %in) {
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; CHECK-LABEL: test_fccmp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #24576
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; CHECK-NEXT: fmov s0, w1
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; CHECK-NEXT: movk w8, #15974, lsl #16
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: mov w8, #16384
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; CHECK-NEXT: movk w8, #15428, lsl #16
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: fmov s2, w8
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; CHECK-NEXT: mov w8, #4
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; CHECK-NEXT: fccmp s0, s2, #8, pl
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; CHECK-NEXT: csinc w8, w8, wzr, mi
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cinc w0, w8, pl
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; CHECK-NEXT: ret
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%f16 = bitcast i16 %in to half
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%cmp0 = fcmp ogt half 0xH3333, %f16
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%cmp1 = fcmp ogt half 0xH2222, %f16
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%x = select i1 %cmp0, i16 0, i16 1
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%or = or i1 %cmp1, %cmp0
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%y = select i1 %or, i16 4, i16 1
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%r = add i16 %x, %y
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ret i16 %r
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}
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