1721ff1dfd
This option was added in D89854. It prevents GVN from performing load PRE in a loop, if doing so would require critical edge splitting on the backedge. From the review: > I know that GVN Load PRE negatively impacts peeling, > loop predication, so the passes expecting that latch has > a conditional branch. In the PhaseOrdering test in this patch, splitting the backedge negatively affects vectorization: After critical edge splitting, the loop gets rotated, effectively peeling off the first loop iteration. The effect is that the first element is handled separately, then the bulk of the elements use a vectorized reduction (but using unaligned, off-by-one memory accesses) and then a tail of 15 elements is handled separately again. It's probably worth noting that the loop load PRE from D99926 is not affected by this change (as it does not need backedge splitting). This is about normal load PRE that happens to occur inside a loop. Differential Revision: https://reviews.llvm.org/D126382
218 lines
7.1 KiB
LLVM
218 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; Tests that check our handling of volatile instructions encountered
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; when scanning for dependencies
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; RUN: opt -basic-aa -gvn -enable-split-backedge-in-load-pre -S < %s | FileCheck %s
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; Check that we can bypass a volatile load when searching
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; for dependencies of a non-volatile load
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define i32 @test1(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%x = load i32, i32* %p
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load volatile i32, i32* %q
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%y = load i32, i32* %p
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; We can not value forward if the query instruction is
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; volatile, this would be (in effect) removing the volatile load
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define i32 @test2(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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%y = load volatile i32, i32* %p
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; If the query instruction is itself volatile, we *cannot*
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; reorder it even if p and q are noalias
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define i32 @test3(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
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; CHECK-NEXT: [[Y:%.*]] = load volatile i32, i32* [[P]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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load volatile i32, i32* %q
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%y = load volatile i32, i32* %p
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; If an encountered instruction is both volatile and ordered,
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; we need to use the strictest ordering of either. In this
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; case, the ordering prevents forwarding.
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define i32 @test4(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[TMP0:%.*]] = load atomic volatile i32, i32* [[Q:%.*]] seq_cst, align 4
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; CHECK-NEXT: [[Y:%.*]] = load atomic i32, i32* [[P]] seq_cst, align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%x = load i32, i32* %p
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load atomic volatile i32, i32* %q seq_cst, align 4
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%y = load atomic i32, i32* %p seq_cst, align 4
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; Value forwarding from a volatile load is perfectly legal
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define i32 @test5(i32* nocapture %p, i32* nocapture %q) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%x = load volatile i32, i32* %p
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%y = load i32, i32* %p
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; Does cross block redundancy elimination work with volatiles?
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define i32 @test6(i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y1]], [[X]]
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; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
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; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%y1 = load i32, i32* %p
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call void @use(i32 %y1)
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br label %header
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header:
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%x = load volatile i32, i32* %q
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%y = load i32, i32* %p
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%add = sub i32 %y, %x
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%cnd = icmp eq i32 %add, 0
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br i1 %cnd, label %exit, label %header
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exit:
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ret i32 %add
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}
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; Does cross block PRE work with volatiles?
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define i32 @test7(i1 %c, i32* noalias nocapture %p, i32* noalias nocapture %q) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[ENTRY_HEADER_CRIT_EDGE:%.*]], label [[SKIP:%.*]]
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; CHECK: entry.header_crit_edge:
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; CHECK-NEXT: [[Y_PRE:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: skip:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P]], align 4
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: header:
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; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[SKIP]] ]
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: [[CND:%.*]] = icmp eq i32 [[ADD]], 0
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; CHECK-NEXT: br i1 [[CND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br i1 %c, label %header, label %skip
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skip:
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%y1 = load i32, i32* %p
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call void @use(i32 %y1)
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br label %header
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header:
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%x = load volatile i32, i32* %q
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%y = load i32, i32* %p
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%add = sub i32 %y, %x
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%cnd = icmp eq i32 %add, 0
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br i1 %cnd, label %exit, label %header
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exit:
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ret i32 %add
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}
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; Another volatile PRE case - two paths through a loop
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; load in preheader, one path read only, one not
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define i32 @test8(i1 %b, i1 %c, i32* noalias %p, i32* noalias %q) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[Y1:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: call void @use(i32 [[Y1]])
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[Y:%.*]] = phi i32 [ [[Y_PRE:%.*]], [[SKIP_HEADER_CRIT_EDGE:%.*]] ], [ [[Y]], [[HEADER]] ], [ [[Y1]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[X:%.*]] = load volatile i32, i32* [[Q:%.*]], align 4
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; CHECK-NEXT: call void @use(i32 [[Y]])
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; CHECK-NEXT: br i1 [[B:%.*]], label [[SKIP:%.*]], label [[HEADER]]
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; CHECK: skip:
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; CHECK-NEXT: call void @clobber(i32* [[P]], i32* [[Q]])
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; CHECK-NEXT: br i1 [[C:%.*]], label [[SKIP_HEADER_CRIT_EDGE]], label [[EXIT:%.*]]
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; CHECK: skip.header_crit_edge:
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; CHECK-NEXT: [[Y_PRE]] = load i32, i32* [[P]], align 4
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: [[ADD:%.*]] = sub i32 [[Y]], [[X]]
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; CHECK-NEXT: ret i32 [[ADD]]
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;
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entry:
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%y1 = load i32, i32* %p
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call void @use(i32 %y1)
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br label %header
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header:
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%x = load volatile i32, i32* %q
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%y = load i32, i32* %p
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call void @use(i32 %y)
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br i1 %b, label %skip, label %header
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skip:
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; escaping the arguments is explicitly required since we marked
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; them noalias
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call void @clobber(i32* %p, i32* %q)
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br i1 %c, label %header, label %exit
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exit:
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%add = sub i32 %y, %x
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ret i32 %add
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}
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; This test checks that we don't optimize away instructions that are
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; simplified by SimplifyInstruction(), but are not trivially dead.
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define i32 @test9(i32* %V) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOAD:%.*]] = call i32 undef()
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; CHECK-NEXT: ret i32 poison
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;
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entry:
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%load = call i32 undef()
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ret i32 %load
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}
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declare void @use(i32) readonly
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declare void @clobber(i32* %p, i32* %q)
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!0 = !{ i32 0, i32 1 }
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