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llvm-project/llvm/lib/Target/RISCV
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Hsiangkai Wang 44cd03ad04 [RISCV] Use register class VR for V instruction operands directly. 
@tangxingxin1008 found a bug that regard vadd.vv v1, v3, a0 as a valid V
instruction. We should remove the VRegAsmOperand operand class and use
VR register class directly.

Patched by: tangxingxin1008, Hsiangkai
Differential Revision: https://reviews.llvm.org/D91712
2020-11-19 05:59:46 +08:00
..
AsmParser
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Disassembler
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
MCTargetDesc
[AsmWriter] Factor out mnemonic generation to accessible getMnemonic.
2020-11-17 09:47:38 +00:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
RISCV.h
[RISCV] Split the pseudo instruction splitting pass
2020-06-29 14:35:57 +01:00
RISCV.td
[RISCV] Add isel patterns for using PACK for zext.h and zext.w.
2020-11-09 10:13:45 -08:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVInstrFormats.td
Upgrade MC to v0.9.
2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] add the MC layer support of riscv vector Zvamo extension
2020-08-27 14:11:38 +08:00
RISCVInstrInfo.cpp
[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
2020-11-03 03:55:47 +00:00
RISCVInstrInfo.h
[RISCV] Don't include CodeGen layer files in MC layer
2020-11-12 07:45:38 -08:00
RISCVInstrInfo.td
[RISCV] Remove traces of Glue from RISCVISD::SELECT_CC
2020-11-11 09:30:48 -08:00
RISCVInstrInfoA.td
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td
[RISCV] Add an ANDI to shift amount of FSL/FSR instructions
2020-11-12 07:33:40 -08:00
RISCVInstrInfoC.td
[RISC-V] Mark C_MV as a move instruction
2020-08-27 10:32:23 +01:00
RISCVInstrInfoD.td
[RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first.
2020-11-05 14:00:25 -08:00
RISCVInstrInfoF.td
[RISCV] Only enable GPR<->FPR32 bitconvert isel patterns on RV32. NFCI
2020-11-05 16:15:25 -08:00
RISCVInstrInfoM.td
[RISCV] Scheduler description for the Rocket core
2020-01-23 19:36:47 -06:00
RISCVInstrInfoV.td
[RISCV] Use register class VR for V instruction operands directly.
2020-11-19 05:59:46 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp
[RISCV] When matching SROIW, check all 64 bits of the OR mask
2020-11-16 10:08:15 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add missing patterns for rotr with immediate for Zbb/Zbp extensions.
2020-11-03 10:04:52 -08:00
RISCVISelLowering.cpp
[RISCV] Use a macro to simplify getTargetNodeName
2020-11-16 09:33:47 +00:00
RISCVISelLowering.h
[RISCV] Make ctlz/cttz cheap to speculatively execute so CodeGenPrepare won't insert a zero check.
2020-11-09 10:13:45 -08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
RISCVMCInstLower.cpp
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
2020-09-03 20:01:23 +08:00
RISCVRegisterBankInfo.cpp
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h
Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"
2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVRegisterInfo.h
CodeGen: More conversions to use Register
2020-04-07 18:54:36 -04:00
RISCVRegisterInfo.td
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
2020-10-02 17:20:34 +08:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSubtarget.h
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00