173ecab705
I just learned that target triples prevent test cases to be run on other architectures. Polly test cases are until now sufficiently target independent to not require any target triples. Hence, we drop them. llvm-svn: 235384
73 lines
2.7 KiB
LLVM
73 lines
2.7 KiB
LLVM
; RUN: opt %loadPolly -polly-detect-unprofitable -basicaa -polly-codegen-isl -polly-vectorizer=polly -dce -S < %s | FileCheck %s
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;#define N 1024
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;float A[N];
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;float B[N];
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;
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;void simple_vec_stride_x(void) {
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; int i;
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;
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; for (i = 0; i < 4; i++)
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; B[2 * i] = A[2 * i];
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;}
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;int main()
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;{
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; simple_vec_stride_x();
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; return A[42];
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;}
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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@A = common global [1024 x float] zeroinitializer, align 16
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@B = common global [1024 x float] zeroinitializer, align 16
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define void @simple_vec_stride_x() nounwind {
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bb:
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br label %bb2
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bb2: ; preds = %bb5, %bb
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%indvar = phi i64 [ %indvar.next, %bb5 ], [ 0, %bb ]
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%tmp = mul i64 %indvar, 2
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%scevgep = getelementptr [1024 x float], [1024 x float]* @B, i64 0, i64 %tmp
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%scevgep1 = getelementptr [1024 x float], [1024 x float]* @A, i64 0, i64 %tmp
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%exitcond = icmp ne i64 %indvar, 4
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br i1 %exitcond, label %bb3, label %bb6
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bb3: ; preds = %bb2
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%tmp4 = load float, float* %scevgep1, align 8
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store float %tmp4, float* %scevgep, align 8
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br label %bb5
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bb5: ; preds = %bb3
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%indvar.next = add i64 %indvar, 1
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br label %bb2
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bb6: ; preds = %bb2
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ret void
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}
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define i32 @main() nounwind {
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bb:
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call void @simple_vec_stride_x()
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%tmp = load float, float* getelementptr inbounds ([1024 x float], [1024 x float]* @A, i64 0, i64 42), align 8
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%tmp1 = fptosi float %tmp to i32
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ret i32 %tmp1
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}
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; CHECK: [[LOAD1:%[a-zA-Z0-9_]+_scalar_]] = load float, float*
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; CHECK: [[VEC1:%[a-zA-Z0-9_]+]] = insertelement <4 x float> undef, float [[LOAD1]], i32 0
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; CHECK: [[LOAD2:%[a-zA-Z0-9_]+]] = load float, float*
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; CHECK: [[VEC2:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC1]], float [[LOAD2]], i32 1
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; CHECK: [[LOAD3:%[a-zA-Z0-9_]+]] = load float, float*
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; CHECK: [[VEC3:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC2]], float [[LOAD3]], i32 2
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; CHECK: [[LOAD4:%[a-zA-Z0-9_]+]] = load float, float*
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; CHECK: [[VEC4:%[a-zA-Z0-9_]+]] = insertelement <4 x float> [[VEC3]], float [[LOAD4]], i32 3
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; CHECK: [[EL1:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 0
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; CHECK: store float [[EL1]]
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; CHECK: [[EL2:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 1
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; CHECK: store float [[EL2]]
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; CHECK: [[EL3:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 2
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; CHECK: store float [[EL3]]
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; CHECK: [[EL4:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 3
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; CHECK: store float [[EL4]]
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