cb3fbe921b
Non-entry functions were unconditionally aligned to 4 bytes with no architecture-specific preferred alignment, and setAlignment() was used instead of ensureAlignment(), overwriting any explicit IR attributes. Add instruction cache line size and fetch alignment data to GCNSubtarget for each generation (GFX9: 64B/32B, GFX10: 64B/4B, GFX11+: 128B/4B). Use this to call setPrefFunctionAlignment() in SITargetLowering, aligning non-entry functions to the cache line size by default. Change setAlignment to ensureAlignment in AMDGPUAsmPrinter so explicit IR align attributes are respected. Empirical thread trace analysis on gfx942, gfx1030, gfx1100, and gfx1200 showed that only GFX9 exhibits measurable fetch stalls when functions cross the 32-byte fetch window boundary. GFX10+ showed no alignment sensitivity. A hidden option -amdgpu-align-functions-for-fetch-only is provided to use the fetch granularity instead of cache line size. Assisted-by: Claude Opus
73 lines
2.4 KiB
LLVM
73 lines
2.4 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA-CI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA-VI %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck --check-prefix=ELF %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa --amdhsa-code-object-version=4 -mcpu=kaveri | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF
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; The SHT_NOTE section contains the output from the .hsa_code_object_*
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; directives.
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; ELF: Section {
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; ELF: Name: .text
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; ELF: Type: SHT_PROGBITS (0x1)
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; ELF: Flags [ (0x6)
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; ELF: SHF_ALLOC (0x2)
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; ELF: SHF_EXECINSTR (0x4)
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; ELF: AddressAlignment: 64
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; ELF: }
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; ELF: SHT_NOTE
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; ELF: 0000: 07000000 4F000000 20000000 414D4447
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; ELF: 0010: 50550000 83AE616D 64687361 2E6B6572
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; ELF: 0020: 6E656C73 90AD616D 64687361 2E746172
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; ELF: 0030: 676574BD 616D6467 636E2D75 6E6B6E6F
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; ELF: 0040: 776E2D61 6D646873 612D2D67 66783730
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; ELF: 0050: 30AE616D 64687361 2E766572 73696F6E
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; ELF: 0060: 92010100
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; ELF: Symbol {
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; ELF: Name: simple
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; ELF: Size: 36
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; ELF: Type: Function (0x2)
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; ELF: }
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; HSA: .text
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; HSA-CI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
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; HSA-VI: .amdgcn_target "amdgcn-unknown-amdhsa--gfx801"
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; HSA-NOT: .amdgpu_hsa_kernel simple
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; HSA: .globl simple
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; HSA: .p2align 6
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; HSA: {{^}}simple:
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; HSA-NOT: amd_kernel_code_t
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; HSA: flat_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[0:1]
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; Make sure we are setting the ATC bit:
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; Make sure we generate flat store for HSA
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; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
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; HSA: .Lfunc_end0:
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; HSA: .size simple, .Lfunc_end0-simple
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; HSA: ; Function info:
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; HSA-NOT: COMPUTE_PGM_RSRC2
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define void @simple(ptr addrspace(4) %ptr.out) {
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entry:
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%out = load ptr addrspace(1), ptr addrspace(4) %ptr.out
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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; Ignore explicit alignment that is too low.
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; HSA: .globl simple_align2
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; HSA: .p2align 6
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define void @simple_align2(ptr addrspace(4) %ptr.out) align 2 {
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entry:
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%out = load ptr addrspace(1), ptr addrspace(4) %ptr.out
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store i32 0, ptr addrspace(1) %out
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ret void
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}
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}
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