2502e3b7ba
Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first class denormal_fpenv attribute. Previously the query for the effective denormal mode involved two string attribute queries with parsing. I'm introducing more uses of this, so it makes sense to convert this to a more efficient encoding. The old representation was also awkward since it was split across two separate attributes. The new encoding just stores the default and float modes as bitfields, largely avoiding the need to consider if the other mode is set. The syntax in the common cases looks like this: `denormal_fpenv(preservesign,preservesign)` `denormal_fpenv(float: preservesign,preservesign)` `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)` I wasn't sure about reusing the float type name instead of adding a new keyword. It's parsed as a type but only accepts float. I'm also debating switching the name to subnormal to match the current preferred IEEE terminology (also used by nofpclass and other contexts). This has a behavior change when using the command flag debug options to set the denormal mode. The behavior of the flag ignored functions with an explicit attribute set, per the default and f32 version. Now that these are one attribute, the flag logic can't distinguish which of the two components were explicitly set on the function. Only one test appeared to rely on this behavior, so I just avoided using the flags in it. This also does not perform all the code cleanups this enables. In particular the attributor handling could be cleaned up. I also guessed at how to support this in MLIR. I followed MemoryEffects as a reference; it appears bitfields are expanded into arguments to attributes, so the representation there is a bit uglier with the 2 2-element fields flattened into 4 arguments.
1344 lines
47 KiB
LLVM
1344 lines
47 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=SI %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=VI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-FAKE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-FAKE16 %s
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; IEEE bit enabled for compute kernel, so shouldn't use.
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define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
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; SI-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
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; SI-NEXT: v_mul_f32_e32 v2, 0.5, v2
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dword v3, v[0:1]
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_f32_e32 v2, 1.0, v3
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; VI-NEXT: v_mul_f32_e32 v2, 0.5, v2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GFX12-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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%a = load float, ptr addrspace(1) %gep0
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, ptr addrspace(1) %out.gep
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ret void
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}
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; IEEE bit enabled for compute kernel, so shouldn't use.
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define amdgpu_kernel void @v_omod_div2_f64_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {
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; SI-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
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; SI-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
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; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
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; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
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; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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; VI-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
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; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]
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; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]
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; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
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%a = load double, ptr addrspace(1) %gep0
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%add = fadd double %a, 1.0
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%div2 = fmul double %add, 0.5
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store double %div2, ptr addrspace(1) %out.gep
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ret void
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}
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; IEEE bit enabled for compute kernel, so shouldn't use even though nsz is allowed
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define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_nsz(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {
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; SI-LABEL: v_omod_div2_f32_enable_ieee_nsz:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
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; SI-NEXT: v_mul_f32_e32 v2, 0.5, v2
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; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: v_omod_div2_f32_enable_ieee_nsz:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dword v3, v[0:1]
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; VI-NEXT: v_mov_b32_e32 v1, s1
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; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_f32_e32 v2, 1.0, v3
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; VI-NEXT: v_mul_f32_e32 v2, 0.5, v2
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; VI-NEXT: flat_store_dword v[0:1], v2
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; VI-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_omod_div2_f32_enable_ieee_nsz:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX11-NEXT: s_endpgm
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;
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; GFX12-LABEL: v_omod_div2_f32_enable_ieee_nsz:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_add_f32_e32 v1, 1.0, v1
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; GFX12-NEXT: v_mul_f32_e32 v1, 0.5, v1
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; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
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; GFX12-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid
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%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
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%a = load float, ptr addrspace(1) %gep0
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, ptr addrspace(1) %out.gep
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ret void
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}
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; IEEE bit enabled for compute kernel, so shouldn't use even though nsz is allowed.
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define amdgpu_kernel void @v_omod_div2_f64_enable_ieee_nsz(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #5 {
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; SI-LABEL: v_omod_div2_f64_enable_ieee_nsz:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, 0
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; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
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; SI-NEXT: v_mov_b32_e32 v1, 0
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
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; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
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; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
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; SI-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
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; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: v_omod_div2_f64_enable_ieee_nsz:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s3
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; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
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; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_div2_f64_enable_ieee_nsz:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_div2_f64_enable_ieee_nsz:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
|
|
; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
; GFX12-NEXT: s_wait_kmcnt 0x0
|
|
; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]
|
|
; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]
|
|
; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]
|
|
; GFX12-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid
|
|
%out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid
|
|
%a = load double, ptr addrspace(1) %gep0
|
|
%add = fadd double %a, 1.0
|
|
%div2 = fmul double %add, 0.5
|
|
store double %div2, ptr addrspace(1) %out.gep
|
|
ret void
|
|
}
|
|
|
|
; Only allow without IEEE bit if signed zeros are significant.
|
|
define amdgpu_ps void @v_omod_div2_f32_signed_zeros(float %a) #4 {
|
|
; SI-LABEL: v_omod_div2_f32_signed_zeros:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f32_signed_zeros:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_f32_signed_zeros:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul float %add, 0.5
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Only allow without IEEE bit if signed zeros are significant.
|
|
define amdgpu_ps void @v_omod_div2_f64_signed_zeros(double %a) #4 {
|
|
; SI-LABEL: v_omod_div2_f64_signed_zeros:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f64_signed_zeros:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_div2_f64_signed_zeros:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_div2_f64_signed_zeros:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd double %a, 1.0
|
|
%div2 = fmul double %add, 0.5
|
|
store double %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_div2_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_div2_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul nsz float %add, 0.5
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_div2_f64(double %a) #5 {
|
|
; SI-LABEL: v_omod_div2_f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_div2_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_div2_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 div:2
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd nsz double %a, 1.0
|
|
%div2 = fmul nsz double %add, 0.5
|
|
store double %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul2_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_mul2_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_mul2_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul nsz float %add, 2.0
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul2_med3(float %x, float %y, float %z) #0 {
|
|
; SI-LABEL: v_omod_mul2_med3:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_med3:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_mul2_med3:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_mul2_med3:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_med3_num_f32 v0, v0, v1, v2 mul:2
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX12-NEXT: s_endpgm
|
|
%fmed3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)
|
|
%div2 = fmul nsz float %fmed3, 2.0
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul2_f64(double %a) #5 {
|
|
; SI-LABEL: v_omod_mul2_f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_mul2_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_mul2_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 mul:2
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd nsz double %a, 1.0
|
|
%div2 = fmul nsz double %add, 2.0
|
|
store double %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul4_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_mul4_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul4_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_mul4_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul nsz float %add, 4.0
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul4_f64(double %a) #5 {
|
|
; SI-LABEL: v_omod_mul4_f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul4_f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_mul4_f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_mul4_f64:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 mul:4
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd nsz double %a, 1.0
|
|
%div2 = fmul nsz double %add, 4.0
|
|
store double %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul4_multi_use_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_mul4_multi_use_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 4.0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul4_multi_use_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_mul_f32_e32 v1, 4.0, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v1
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_mul4_multi_use_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_mul_f32_e32 v1, 4.0, v0
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v1, off
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc
|
|
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_mul4_multi_use_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_mul_f32_e32 v1, 4.0, v0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v1, off
|
|
; GFX12-NEXT: s_wait_storecnt 0x0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_storecnt 0x0
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul float %add, 4.0
|
|
store float %div2, ptr addrspace(1) poison
|
|
store volatile float %add, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mul4_dbg_use_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_mul4_dbg_use_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul4_dbg_use_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_mul4_dbg_use_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10
|
|
%div2 = fmul nsz float %add, 4.0
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Clamp is applied after omod, folding both into instruction is OK.
|
|
define amdgpu_ps void @v_clamp_omod_div2_f32(float %a) #0 {
|
|
; SI-LABEL: v_clamp_omod_div2_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_clamp_omod_div2_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_clamp_omod_div2_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul nsz float %add, 0.5
|
|
|
|
%max = call float @llvm.maxnum.f32(float %div2, float 0.0)
|
|
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
store float %clamp, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Cannot fold omod into clamp
|
|
define amdgpu_ps void @v_omod_div2_clamp_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_div2_clamp_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
|
|
; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_clamp_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
|
|
; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_clamp_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%max = call float @llvm.maxnum.f32(float %add, float 0.0)
|
|
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
%div2 = fmul float %clamp, 0.5
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_div2_abs_src_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_div2_abs_src_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, |v0|, 0.5
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_abs_src_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_mul_f32_e64 v0, |v0|, 0.5
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_abs_src_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_mul_f32_e64 v0, |v0|, 0.5
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%abs.add = call float @llvm.fabs.f32(float %add)
|
|
%div2 = fmul float %abs.add, 0.5
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_add_self_clamp_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_add_self_clamp_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, v0 clamp
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_add_self_clamp_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, v0 clamp
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_add_self_clamp_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, v0 clamp
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, %a
|
|
%max = call float @llvm.maxnum.f32(float %add, float 0.0)
|
|
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
store float %clamp, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_add_clamp_self_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_add_clamp_self_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_max_f32_e64 v0, v0, v0 clamp
|
|
; SI-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_add_clamp_self_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_max_f32_e64 v0, v0, v0 clamp
|
|
; VI-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_add_clamp_self_f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_max_f32_e64 v0, v0, v0 clamp
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; GFX11-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_add_clamp_self_f32:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_max_num_f32_e64 v0, v0, v0 clamp
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX12-NEXT: s_endpgm
|
|
%max = call float @llvm.maxnum.f32(float %a, float 0.0)
|
|
%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
|
|
%add = fadd float %clamp, %clamp
|
|
store float %add, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_add_abs_self_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_add_abs_self_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e64 v0, |v0|, |v0|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_add_abs_self_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_add_f32_e64 v0, |v0|, |v0|
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_add_abs_self_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, |v0|, |v0|
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%x = fadd float %a, 1.0
|
|
%abs.x = call float @llvm.fabs.f32(float %x)
|
|
%add = fadd float %abs.x, %abs.x
|
|
store float %add, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_add_abs_x_x_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_add_abs_x_x_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e64 v0, |v0|, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_add_abs_x_x_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_add_f32_e64 v0, |v0|, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_add_abs_x_x_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, |v0|, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%x = fadd float %a, 1.0
|
|
%abs.x = call float @llvm.fabs.f32(float %x)
|
|
%add = fadd float %abs.x, %x
|
|
store float %add, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_add_x_abs_x_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_add_x_abs_x_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, |v0|
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_add_x_abs_x_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, |v0|
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_add_x_abs_x_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, |v0|
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%x = fadd float %a, 1.0
|
|
%abs.x = call float @llvm.fabs.f32(float %x)
|
|
%add = fadd float %x, %abs.x
|
|
store float %add, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod into omod into another omod.
|
|
define amdgpu_ps void @v_omod_div2_omod_div2_f32(float %a) #0 {
|
|
; SI-LABEL: v_omod_div2_omod_div2_f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_omod_div2_f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_omod_div2_f32:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2.0 = fmul nsz float %add, 0.5
|
|
%div2.1 = fmul float %div2.0, 0.5
|
|
store float %div2.1, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled
|
|
define amdgpu_ps void @v_omod_div2_f32_denormals(float %a) #2 {
|
|
; SI-LABEL: v_omod_div2_f32_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f32_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_div2_f32_denormals:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul float %add, 0.5
|
|
store float %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled.
|
|
define amdgpu_ps void @v_omod_div2_f64_denormals(double %a) #6 {
|
|
; SI-LABEL: v_omod_div2_f64_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f64_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_div2_f64_denormals:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_div2_f64_denormals:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd double %a, 1.0
|
|
%div2 = fmul double %add, 0.5
|
|
store double %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled for add form.
|
|
define amdgpu_ps void @v_omod_mul2_f32_denormals(float %a) #2 {
|
|
; SI-LABEL: v_omod_mul2_f32_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_f32_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_mul2_f32_denormals:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_add_f32_e32 v0, v0, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%mul2 = fadd float %add, %add
|
|
store float %mul2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled for add form.
|
|
define amdgpu_ps void @v_omod_mul2_f64_denormals(double %a) #2 {
|
|
; SI-LABEL: v_omod_mul2_f64_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_f64_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]
|
|
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_omod_mul2_f64_denormals:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: v_omod_mul2_f64_denormals:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[0:1]
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
%add = fadd double %a, 1.0
|
|
%mul2 = fadd double %add, %add
|
|
store double %mul2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled
|
|
define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
|
|
; SI-LABEL: v_omod_div2_f16_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 div:2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f16_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_mul_f16_e32 v0, 0.5, v0
|
|
; VI-NEXT: flat_store_short v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-TRUE16-LABEL: v_omod_div2_f16_denormals:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.5, v0.l
|
|
; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX11-FAKE16-LABEL: v_omod_div2_f16_denormals:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, 0.5, v0
|
|
; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-TRUE16-LABEL: v_omod_div2_f16_denormals:
|
|
; GFX12-TRUE16: ; %bb.0:
|
|
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
|
|
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.5, v0.l
|
|
; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-FAKE16-LABEL: v_omod_div2_f16_denormals:
|
|
; GFX12-FAKE16: ; %bb.0:
|
|
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-FAKE16-NEXT: v_mul_f16_e32 v0, 0.5, v0
|
|
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-FAKE16-NEXT: s_endpgm
|
|
%add = fadd half %a, 1.0
|
|
%div2 = fmul nsz half %add, 0.5
|
|
store half %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
; Don't fold omod if denorms enabled for add form.
|
|
define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
|
|
; SI-LABEL: v_omod_mul2_f16_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 mul:2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mul2_f16_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; VI-NEXT: v_add_f16_e32 v0, v0, v0
|
|
; VI-NEXT: flat_store_short v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-TRUE16-LABEL: v_omod_mul2_f16_denormals:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l
|
|
; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX11-FAKE16-LABEL: v_omod_mul2_f16_denormals:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v0
|
|
; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-TRUE16-LABEL: v_omod_mul2_f16_denormals:
|
|
; GFX12-TRUE16: ; %bb.0:
|
|
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l
|
|
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l
|
|
; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-FAKE16-LABEL: v_omod_mul2_f16_denormals:
|
|
; GFX12-FAKE16: ; %bb.0:
|
|
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v0
|
|
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v0, v0
|
|
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-FAKE16-NEXT: s_endpgm
|
|
%add = fadd half %a, 1.0
|
|
%mul2 = fadd nsz half %add, %add
|
|
store half %mul2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {
|
|
; SI-LABEL: v_omod_div2_f16_no_denormals:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 div:2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_div2_f16_no_denormals:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f16_e64 v0, v0, 1.0 div:2
|
|
; VI-NEXT: flat_store_short v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11-TRUE16-LABEL: v_omod_div2_f16_no_denormals:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, v0.l, 1.0 div:2
|
|
; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX11-FAKE16-LABEL: v_omod_div2_f16_no_denormals:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, v0, 1.0 div:2
|
|
; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX11-FAKE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-TRUE16-LABEL: v_omod_div2_f16_no_denormals:
|
|
; GFX12-TRUE16: ; %bb.0:
|
|
; GFX12-TRUE16-NEXT: v_add_f16_e64 v0.l, v0.l, 1.0 div:2
|
|
; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-TRUE16-NEXT: s_endpgm
|
|
;
|
|
; GFX12-FAKE16-LABEL: v_omod_div2_f16_no_denormals:
|
|
; GFX12-FAKE16: ; %bb.0:
|
|
; GFX12-FAKE16-NEXT: v_add_f16_e64 v0, v0, 1.0 div:2
|
|
; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
|
|
; GFX12-FAKE16-NEXT: s_endpgm
|
|
%add = fadd half %a, 1.0
|
|
%div2 = fmul nsz half %add, 0.5
|
|
store half %div2, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_omod_mac_to_mad(float %b, float %a) #0 {
|
|
; SI-LABEL: v_omod_mac_to_mad:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_mad_f32 v1, v1, v1, v0 mul:2
|
|
; SI-NEXT: v_mul_f32_e32 v0, v1, v0
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_omod_mac_to_mad:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_mad_f32 v1, v1, v1, v0 mul:2
|
|
; VI-NEXT: v_mul_f32_e32 v0, v1, v0
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_omod_mac_to_mad:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v1, v1, v1
|
|
; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v1, v1, v0 mul:2
|
|
; GFX11PLUS-NEXT: v_mul_f32_e32 v0, v1, v0
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%mul = fmul float %a, %a
|
|
%add = fadd float %mul, %b
|
|
%mad = fmul nsz float %add, 2.0
|
|
%res = fmul float %mad, %b
|
|
store float %res, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @v_clamp_omod_div2_f32_minimumnum_maximumnum(float %a) #0 {
|
|
; SI-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; SI-NEXT: s_mov_b32 s3, 0xf000
|
|
; SI-NEXT: s_mov_b32 s2, -1
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; SI-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; VI-NEXT: flat_store_dword v[0:1], v0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX11PLUS-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:
|
|
; GFX11PLUS: ; %bb.0:
|
|
; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2
|
|
; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off
|
|
; GFX11PLUS-NEXT: s_endpgm
|
|
%add = fadd float %a, 1.0
|
|
%div2 = fmul nsz float %add, 0.5
|
|
|
|
%max = call float @llvm.maximumnum.f32(float %div2, float 0.0)
|
|
%clamp = call float @llvm.minimumnum.f32(float %max, float 1.0)
|
|
store float %clamp, ptr addrspace(1) poison
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
declare float @llvm.fabs.f32(float) #1
|
|
declare float @llvm.floor.f32(float) #1
|
|
declare float @llvm.minnum.f32(float, float) #1
|
|
declare float @llvm.maxnum.f32(float, float) #1
|
|
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
|
|
declare double @llvm.fabs.f64(double) #1
|
|
declare double @llvm.minnum.f64(double, double) #1
|
|
declare double @llvm.maxnum.f64(double, double) #1
|
|
declare half @llvm.fabs.f16(half) #1
|
|
declare half @llvm.minnum.f16(half, half) #1
|
|
declare half @llvm.maxnum.f16(half, half) #1
|
|
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
|
|
|
|
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
|
|
attributes #1 = { nounwind readnone }
|
|
attributes #2 = { nounwind denormal_fpenv(float: ieee) }
|
|
attributes #3 = { nounwind denormal_fpenv(preservesign) }
|
|
attributes #4 = { nounwind "no-signed-zeros-fp-math"="false" }
|
|
attributes #5 = { nounwind denormal_fpenv(preservesign) }
|
|
attributes #6 = { nounwind denormal_fpenv(ieee) }
|
|
|
|
!llvm.dbg.cu = !{!0}
|
|
!llvm.module.flags = !{!2, !3}
|
|
|
|
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug)
|
|
!1 = !DIFile(filename: "/tmp/foo.cl", directory: "/dev/null")
|
|
!2 = !{i32 2, !"Dwarf Version", i32 4}
|
|
!3 = !{i32 2, !"Debug Info Version", i32 3}
|
|
!4 = !DILocalVariable(name: "add", arg: 1, scope: !5, file: !1, line: 1)
|
|
!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
|
|
!6 = !DISubroutineType(types: !7)
|
|
!7 = !{null, !8}
|
|
!8 = !DIBasicType(name: "float", size: 32, align: 32)
|
|
!9 = !DIExpression()
|
|
!10 = !DILocation(line: 1, column: 42, scope: !5)
|