a97f5ec95f
Fix ABI on old subtargets so match new subtargets, packing 16-bit element subvectors into 32-bit registers. Previously this would be scalarized and promoted to i32/float. Note this only changes the vector cases. Scalar i16/half are still promoted to i32/float for now. I've unsuccessfully tried to make that switch in the past, so leave that for later. This will help with removal of softPromoteHalfType.
37 lines
1006 B
LLVM
37 lines
1006 B
LLVM
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck %s
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; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck %s
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@global = addrspace(1) global i32 poison, align 4
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; The hardware initializes the registers received as arguments by entry points,
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; so they will be counted even if unused.
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; Vectors of i1 are always unpacked
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; CHECK-LABEL: vec_of_i1:
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; CHECK: TotalNumSgprs: 8
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define amdgpu_ps void @vec_of_i1(<8 x i1> inreg %v8i1) {
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ret void
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}
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; Vectors of i8 are always unpacked
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; CHECK-LABEL: vec_of_i8:
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; CHECK: TotalNumSgprs: 4
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define amdgpu_ps void @vec_of_i8(<4 x i8> inreg %v4i8) {
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ret void
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}
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; Vectors of 16-bit types are packed.
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; CHECK-LABEL: vec_of_16_bit_ty:
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; CHECK: TotalNumSgprs: 3
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define amdgpu_ps void @vec_of_16_bit_ty(<2 x i16> inreg %v2i16, <4 x half> inreg %v4half) {
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ret void
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}
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; CHECK-LABEL: buffer_fat_ptr:
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; CHECK: TotalNumSgprs: 5
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define amdgpu_ps void @buffer_fat_ptr(ptr addrspace(7) inreg %p) {
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ret void
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}
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