af95b0a615
The mov64 pseudo is split into two 32 bit movs, but those 32 bit movs had the full 64-bit register still implicitly defined. VOPD formation is affected, so we can emit more of them.
21 lines
720 B
LLVM
21 lines
720 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
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define amdgpu_kernel void @foo(ptr %0) {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: v_mov_b32_e32 v5, 0
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; CHECK-NEXT: v_mov_b32_e32 v6, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
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; CHECK-NEXT: flat_store_dwordx3 v[2:3], v[4:6]
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; CHECK-NEXT: s_endpgm
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entry:
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%1 = getelementptr inbounds i8, ptr %0, i64 4
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store i32 0, ptr %0, align 4
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store i64 0, ptr %1, align 4
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ret void
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}
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