f9c98068c8
This PR contains changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. This potentially helps to detect previously missed flaws in code emission and harden the test suite. As a measure of correctness and usefulness of this PR we may use a mode with expensive checks set on, and MachineVerifier reports problems in the test suite. In order to satisfy Machine Verifier requirements to MIR correctness not only a rework of usage of virtual registers' types and classes is required, but also corrections into pre-legalizer and instruction selection logics. Namely, the following changes are introduced: * scalar virtual registers have proper bit width, * detect register class by SPIR-V type, * add a superclass for id virtual register classes, * fix Tablegen rules used for instruction selection, * fixes of minor existed issues (missed flag for proper representation of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual registers as a synonym of any non-type virtual register).
469 lines
20 KiB
C++
469 lines
20 KiB
C++
//===- SPIRVISelLowering.cpp - SPIR-V DAG Lowering Impl ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SPIRVTargetLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRVISelLowering.h"
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#include "SPIRV.h"
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#include "SPIRVInstrInfo.h"
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#include "SPIRVRegisterBankInfo.h"
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#include "SPIRVRegisterInfo.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#define DEBUG_TYPE "spirv-lower"
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using namespace llvm;
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unsigned SPIRVTargetLowering::getNumRegistersForCallingConv(
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LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
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// This code avoids CallLowering fail inside getVectorTypeBreakdown
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// on v3i1 arguments. Maybe we need to return 1 for all types.
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// TODO: remove it once this case is supported by the default implementation.
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if (VT.isVector() && VT.getVectorNumElements() == 3 &&
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(VT.getVectorElementType() == MVT::i1 ||
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VT.getVectorElementType() == MVT::i8))
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return 1;
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if (!VT.isVector() && VT.isInteger() && VT.getSizeInBits() <= 64)
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return 1;
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return getNumRegisters(Context, VT);
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}
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MVT SPIRVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
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CallingConv::ID CC,
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EVT VT) const {
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// This code avoids CallLowering fail inside getVectorTypeBreakdown
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// on v3i1 arguments. Maybe we need to return i32 for all types.
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// TODO: remove it once this case is supported by the default implementation.
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if (VT.isVector() && VT.getVectorNumElements() == 3) {
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if (VT.getVectorElementType() == MVT::i1)
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return MVT::v4i1;
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else if (VT.getVectorElementType() == MVT::i8)
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return MVT::v4i8;
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}
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return getRegisterType(Context, VT);
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}
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bool SPIRVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const {
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unsigned AlignIdx = 3;
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switch (Intrinsic) {
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case Intrinsic::spv_load:
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AlignIdx = 2;
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[[fallthrough]];
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case Intrinsic::spv_store: {
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if (I.getNumOperands() >= AlignIdx + 1) {
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auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));
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Info.align = Align(AlignOp->getZExtValue());
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}
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Info.flags = static_cast<MachineMemOperand::Flags>(
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cast<ConstantInt>(I.getOperand(AlignIdx - 1))->getZExtValue());
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Info.memVT = MVT::i64;
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// TODO: take into account opaque pointers (don't use getElementType).
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// MVT::getVT(PtrTy->getElementType());
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return true;
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break;
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}
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default:
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break;
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}
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return false;
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}
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std::pair<unsigned, const TargetRegisterClass *>
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SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint,
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MVT VT) const {
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const TargetRegisterClass *RC = nullptr;
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if (Constraint.starts_with("{"))
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return std::make_pair(0u, RC);
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if (VT.isFloatingPoint())
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RC = VT.isVector() ? &SPIRV::vfIDRegClass
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: (VT.getScalarSizeInBits() > 32 ? &SPIRV::fID64RegClass
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: &SPIRV::fIDRegClass);
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else if (VT.isInteger())
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RC = VT.isVector() ? &SPIRV::vIDRegClass
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: (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
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: &SPIRV::iIDRegClass);
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else
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RC = &SPIRV::iIDRegClass;
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return std::make_pair(0u, RC);
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}
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inline Register getTypeReg(MachineRegisterInfo *MRI, Register OpReg) {
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SPIRVType *TypeInst = MRI->getVRegDef(OpReg);
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return TypeInst && TypeInst->getOpcode() == SPIRV::OpFunctionParameter
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? TypeInst->getOperand(1).getReg()
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: OpReg;
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}
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static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
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SPIRVGlobalRegistry &GR, MachineInstr &I,
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Register OpReg, unsigned OpIdx,
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SPIRVType *NewPtrType) {
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Register NewReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
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MachineIRBuilder MIB(I);
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bool Res = MIB.buildInstr(SPIRV::OpBitcast)
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.addDef(NewReg)
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.addUse(GR.getSPIRVTypeID(NewPtrType))
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.addUse(OpReg)
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.constrainAllUses(*STI.getInstrInfo(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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if (!Res)
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report_fatal_error("insert validation bitcast: cannot constrain all uses");
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MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
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GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
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I.getOperand(OpIdx).setReg(NewReg);
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}
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static SPIRVType *createNewPtrType(SPIRVGlobalRegistry &GR, MachineInstr &I,
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SPIRVType *OpType, bool ReuseType,
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bool EmitIR, SPIRVType *ResType,
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const Type *ResTy) {
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SPIRV::StorageClass::StorageClass SC =
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static_cast<SPIRV::StorageClass::StorageClass>(
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OpType->getOperand(1).getImm());
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MachineIRBuilder MIB(I);
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SPIRVType *NewBaseType =
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ReuseType ? ResType
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: GR.getOrCreateSPIRVType(
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ResTy, MIB, SPIRV::AccessQualifier::ReadWrite, EmitIR);
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return GR.getOrCreateSPIRVPointerType(NewBaseType, MIB, SC);
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}
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// Insert a bitcast before the instruction to keep SPIR-V code valid
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// when there is a type mismatch between results and operand types.
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static void validatePtrTypes(const SPIRVSubtarget &STI,
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MachineRegisterInfo *MRI, SPIRVGlobalRegistry &GR,
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MachineInstr &I, unsigned OpIdx,
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SPIRVType *ResType, const Type *ResTy = nullptr) {
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// Get operand type
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MachineFunction *MF = I.getParent()->getParent();
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Register OpReg = I.getOperand(OpIdx).getReg();
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Register OpTypeReg = getTypeReg(MRI, OpReg);
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SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
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if (!ResType || !OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
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return;
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// Get operand's pointee type
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Register ElemTypeReg = OpType->getOperand(2).getReg();
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SPIRVType *ElemType = GR.getSPIRVTypeForVReg(ElemTypeReg, MF);
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if (!ElemType)
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return;
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// Check if we need a bitcast to make a statement valid
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bool IsSameMF = MF == ResType->getParent()->getParent();
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bool IsEqualTypes = IsSameMF ? ElemType == ResType
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: GR.getTypeForSPIRVType(ElemType) == ResTy;
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if (IsEqualTypes)
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return;
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// There is a type mismatch between results and operand types
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// and we insert a bitcast before the instruction to keep SPIR-V code valid
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SPIRVType *NewPtrType =
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createNewPtrType(GR, I, OpType, IsSameMF, false, ResType, ResTy);
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if (!GR.isBitcastCompatible(NewPtrType, OpType))
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report_fatal_error(
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"insert validation bitcast: incompatible result and operand types");
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doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
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}
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// Insert a bitcast before OpGroupWaitEvents if the last argument is a pointer
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// that doesn't point to OpTypeEvent.
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static void validateGroupWaitEventsPtr(const SPIRVSubtarget &STI,
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MachineRegisterInfo *MRI,
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SPIRVGlobalRegistry &GR,
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MachineInstr &I) {
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constexpr unsigned OpIdx = 2;
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MachineFunction *MF = I.getParent()->getParent();
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Register OpReg = I.getOperand(OpIdx).getReg();
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Register OpTypeReg = getTypeReg(MRI, OpReg);
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SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
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if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
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return;
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SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg());
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if (!ElemType || ElemType->getOpcode() == SPIRV::OpTypeEvent)
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return;
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// Insert a bitcast before the instruction to keep SPIR-V code valid.
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LLVMContext &Context = MF->getFunction().getContext();
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SPIRVType *NewPtrType =
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createNewPtrType(GR, I, OpType, false, true, nullptr,
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TargetExtType::get(Context, "spirv.Event"));
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doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
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}
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static void validateLifetimeStart(const SPIRVSubtarget &STI,
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MachineRegisterInfo *MRI,
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SPIRVGlobalRegistry &GR, MachineInstr &I) {
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Register PtrReg = I.getOperand(0).getReg();
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MachineFunction *MF = I.getParent()->getParent();
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Register PtrTypeReg = getTypeReg(MRI, PtrReg);
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SPIRVType *PtrType = GR.getSPIRVTypeForVReg(PtrTypeReg, MF);
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SPIRVType *PonteeElemType = PtrType ? GR.getPointeeType(PtrType) : nullptr;
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if (!PonteeElemType || PonteeElemType->getOpcode() == SPIRV::OpTypeVoid ||
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(PonteeElemType->getOpcode() == SPIRV::OpTypeInt &&
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PonteeElemType->getOperand(1).getImm() == 8))
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return;
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// To keep the code valid a bitcast must be inserted
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SPIRV::StorageClass::StorageClass SC =
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static_cast<SPIRV::StorageClass::StorageClass>(
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PtrType->getOperand(1).getImm());
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MachineIRBuilder MIB(I);
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LLVMContext &Context = MF->getFunction().getContext();
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SPIRVType *ElemType =
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GR.getOrCreateSPIRVType(IntegerType::getInt8Ty(Context), MIB);
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SPIRVType *NewPtrType = GR.getOrCreateSPIRVPointerType(ElemType, MIB, SC);
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doInsertBitcast(STI, MRI, GR, I, PtrReg, 0, NewPtrType);
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}
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static void validateGroupAsyncCopyPtr(const SPIRVSubtarget &STI,
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MachineRegisterInfo *MRI,
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SPIRVGlobalRegistry &GR, MachineInstr &I,
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unsigned OpIdx) {
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MachineFunction *MF = I.getParent()->getParent();
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Register OpReg = I.getOperand(OpIdx).getReg();
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Register OpTypeReg = getTypeReg(MRI, OpReg);
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SPIRVType *OpType = GR.getSPIRVTypeForVReg(OpTypeReg, MF);
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if (!OpType || OpType->getOpcode() != SPIRV::OpTypePointer)
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return;
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SPIRVType *ElemType = GR.getSPIRVTypeForVReg(OpType->getOperand(2).getReg());
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if (!ElemType || ElemType->getOpcode() != SPIRV::OpTypeStruct ||
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ElemType->getNumOperands() != 2)
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return;
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// It's a structure-wrapper around another type with a single member field.
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SPIRVType *MemberType =
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GR.getSPIRVTypeForVReg(ElemType->getOperand(1).getReg());
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if (!MemberType)
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return;
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unsigned MemberTypeOp = MemberType->getOpcode();
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if (MemberTypeOp != SPIRV::OpTypeVector && MemberTypeOp != SPIRV::OpTypeInt &&
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MemberTypeOp != SPIRV::OpTypeFloat && MemberTypeOp != SPIRV::OpTypeBool)
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return;
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// It's a structure-wrapper around a valid type. Insert a bitcast before the
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// instruction to keep SPIR-V code valid.
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SPIRV::StorageClass::StorageClass SC =
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static_cast<SPIRV::StorageClass::StorageClass>(
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OpType->getOperand(1).getImm());
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MachineIRBuilder MIB(I);
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SPIRVType *NewPtrType = GR.getOrCreateSPIRVPointerType(MemberType, MIB, SC);
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doInsertBitcast(STI, MRI, GR, I, OpReg, OpIdx, NewPtrType);
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}
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// Insert a bitcast before the function call instruction to keep SPIR-V code
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// valid when there is a type mismatch between actual and expected types of an
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// argument:
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// %formal = OpFunctionParameter %formal_type
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// ...
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// %res = OpFunctionCall %ty %fun %actual ...
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// implies that %actual is of %formal_type, and in case of opaque pointers.
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// We may need to insert a bitcast to ensure this.
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void validateFunCallMachineDef(const SPIRVSubtarget &STI,
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MachineRegisterInfo *DefMRI,
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MachineRegisterInfo *CallMRI,
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SPIRVGlobalRegistry &GR, MachineInstr &FunCall,
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MachineInstr *FunDef) {
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if (FunDef->getOpcode() != SPIRV::OpFunction)
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return;
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unsigned OpIdx = 3;
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for (FunDef = FunDef->getNextNode();
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FunDef && FunDef->getOpcode() == SPIRV::OpFunctionParameter &&
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OpIdx < FunCall.getNumOperands();
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FunDef = FunDef->getNextNode(), OpIdx++) {
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SPIRVType *DefPtrType = DefMRI->getVRegDef(FunDef->getOperand(1).getReg());
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SPIRVType *DefElemType =
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DefPtrType && DefPtrType->getOpcode() == SPIRV::OpTypePointer
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? GR.getSPIRVTypeForVReg(DefPtrType->getOperand(2).getReg(),
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DefPtrType->getParent()->getParent())
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: nullptr;
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if (DefElemType) {
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const Type *DefElemTy = GR.getTypeForSPIRVType(DefElemType);
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// validatePtrTypes() works in the context if the call site
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// When we process historical records about forward calls
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// we need to switch context to the (forward) call site and
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// then restore it back to the current machine function.
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MachineFunction *CurMF =
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GR.setCurrentFunc(*FunCall.getParent()->getParent());
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validatePtrTypes(STI, CallMRI, GR, FunCall, OpIdx, DefElemType,
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DefElemTy);
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GR.setCurrentFunc(*CurMF);
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}
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}
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}
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// Ensure there is no mismatch between actual and expected arg types: calls
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// with a processed definition. Return Function pointer if it's a forward
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// call (ahead of definition), and nullptr otherwise.
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const Function *validateFunCall(const SPIRVSubtarget &STI,
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MachineRegisterInfo *CallMRI,
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SPIRVGlobalRegistry &GR,
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MachineInstr &FunCall) {
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const GlobalValue *GV = FunCall.getOperand(2).getGlobal();
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const Function *F = dyn_cast<Function>(GV);
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MachineInstr *FunDef =
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const_cast<MachineInstr *>(GR.getFunctionDefinition(F));
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if (!FunDef)
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return F;
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MachineRegisterInfo *DefMRI = &FunDef->getParent()->getParent()->getRegInfo();
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validateFunCallMachineDef(STI, DefMRI, CallMRI, GR, FunCall, FunDef);
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return nullptr;
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}
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// Ensure there is no mismatch between actual and expected arg types: calls
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// ahead of a processed definition.
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void validateForwardCalls(const SPIRVSubtarget &STI,
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MachineRegisterInfo *DefMRI, SPIRVGlobalRegistry &GR,
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MachineInstr &FunDef) {
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const Function *F = GR.getFunctionByDefinition(&FunDef);
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if (SmallPtrSet<MachineInstr *, 8> *FwdCalls = GR.getForwardCalls(F))
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for (MachineInstr *FunCall : *FwdCalls) {
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MachineRegisterInfo *CallMRI =
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&FunCall->getParent()->getParent()->getRegInfo();
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validateFunCallMachineDef(STI, DefMRI, CallMRI, GR, *FunCall, &FunDef);
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}
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}
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// Validation of an access chain.
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void validateAccessChain(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
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SPIRVGlobalRegistry &GR, MachineInstr &I) {
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SPIRVType *BaseTypeInst = GR.getSPIRVTypeForVReg(I.getOperand(0).getReg());
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if (BaseTypeInst && BaseTypeInst->getOpcode() == SPIRV::OpTypePointer) {
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SPIRVType *BaseElemType =
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GR.getSPIRVTypeForVReg(BaseTypeInst->getOperand(2).getReg());
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validatePtrTypes(STI, MRI, GR, I, 2, BaseElemType);
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}
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}
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// TODO: the logic of inserting additional bitcast's is to be moved
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// to pre-IRTranslation passes eventually
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void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const {
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// finalizeLowering() is called twice (see GlobalISel/InstructionSelect.cpp)
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// We'd like to avoid the needless second processing pass.
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if (ProcessedMF.find(&MF) != ProcessedMF.end())
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return;
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry();
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GR.setCurrentFunc(MF);
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
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MBBI != MBBE;) {
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MachineInstr &MI = *MBBI++;
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switch (MI.getOpcode()) {
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case SPIRV::OpAtomicLoad:
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case SPIRV::OpAtomicExchange:
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case SPIRV::OpAtomicCompareExchange:
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case SPIRV::OpAtomicCompareExchangeWeak:
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case SPIRV::OpAtomicIIncrement:
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case SPIRV::OpAtomicIDecrement:
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case SPIRV::OpAtomicIAdd:
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case SPIRV::OpAtomicISub:
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case SPIRV::OpAtomicSMin:
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case SPIRV::OpAtomicUMin:
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case SPIRV::OpAtomicSMax:
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case SPIRV::OpAtomicUMax:
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case SPIRV::OpAtomicAnd:
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case SPIRV::OpAtomicOr:
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case SPIRV::OpAtomicXor:
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// for the above listed instructions
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// OpAtomicXXX <ResType>, ptr %Op, ...
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// implies that %Op is a pointer to <ResType>
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case SPIRV::OpLoad:
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// OpLoad <ResType>, ptr %Op implies that %Op is a pointer to <ResType>
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validatePtrTypes(STI, MRI, GR, MI, 2,
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GR.getSPIRVTypeForVReg(MI.getOperand(0).getReg()));
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break;
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case SPIRV::OpAtomicStore:
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// OpAtomicStore ptr %Op, <Scope>, <Mem>, <Obj>
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// implies that %Op points to the <Obj>'s type
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validatePtrTypes(STI, MRI, GR, MI, 0,
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GR.getSPIRVTypeForVReg(MI.getOperand(3).getReg()));
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break;
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case SPIRV::OpStore:
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// OpStore ptr %Op, <Obj> implies that %Op points to the <Obj>'s type
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validatePtrTypes(STI, MRI, GR, MI, 0,
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GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg()));
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break;
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case SPIRV::OpPtrCastToGeneric:
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case SPIRV::OpGenericCastToPtr:
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validateAccessChain(STI, MRI, GR, MI);
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break;
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case SPIRV::OpInBoundsPtrAccessChain:
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if (MI.getNumOperands() == 4)
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validateAccessChain(STI, MRI, GR, MI);
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break;
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|
|
case SPIRV::OpFunctionCall:
|
|
// ensure there is no mismatch between actual and expected arg types:
|
|
// calls with a processed definition
|
|
if (MI.getNumOperands() > 3)
|
|
if (const Function *F = validateFunCall(STI, MRI, GR, MI))
|
|
GR.addForwardCall(F, &MI);
|
|
break;
|
|
case SPIRV::OpFunction:
|
|
// ensure there is no mismatch between actual and expected arg types:
|
|
// calls ahead of a processed definition
|
|
validateForwardCalls(STI, MRI, GR, MI);
|
|
break;
|
|
|
|
// ensure that LLVM IR bitwise instructions result in logical SPIR-V
|
|
// instructions when applied to bool type
|
|
case SPIRV::OpBitwiseOrS:
|
|
case SPIRV::OpBitwiseOrV:
|
|
if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
|
|
SPIRV::OpTypeBool))
|
|
MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr));
|
|
break;
|
|
case SPIRV::OpBitwiseAndS:
|
|
case SPIRV::OpBitwiseAndV:
|
|
if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
|
|
SPIRV::OpTypeBool))
|
|
MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalAnd));
|
|
break;
|
|
case SPIRV::OpBitwiseXorS:
|
|
case SPIRV::OpBitwiseXorV:
|
|
if (GR.isScalarOrVectorOfType(MI.getOperand(1).getReg(),
|
|
SPIRV::OpTypeBool))
|
|
MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual));
|
|
break;
|
|
case SPIRV::OpLifetimeStart:
|
|
case SPIRV::OpLifetimeStop:
|
|
if (MI.getOperand(1).getImm() > 0)
|
|
validateLifetimeStart(STI, MRI, GR, MI);
|
|
break;
|
|
case SPIRV::OpGroupAsyncCopy:
|
|
validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 3);
|
|
validateGroupAsyncCopyPtr(STI, MRI, GR, MI, 4);
|
|
break;
|
|
case SPIRV::OpGroupWaitEvents:
|
|
// OpGroupWaitEvents ..., ..., <pointer to OpTypeEvent>
|
|
validateGroupWaitEventsPtr(STI, MRI, GR, MI);
|
|
break;
|
|
case SPIRV::OpConstantI: {
|
|
SPIRVType *Type = GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg());
|
|
if (Type->getOpcode() != SPIRV::OpTypeInt && MI.getOperand(2).isImm() &&
|
|
MI.getOperand(2).getImm() == 0) {
|
|
// Validate the null constant of a target extension type
|
|
MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull));
|
|
for (unsigned i = MI.getNumOperands() - 1; i > 1; --i)
|
|
MI.removeOperand(i);
|
|
}
|
|
} break;
|
|
}
|
|
}
|
|
}
|
|
ProcessedMF.insert(&MF);
|
|
TargetLowering::finalizeLowering(MF);
|
|
}
|