cdfd884b0e
Update TableGen specification of DXIL Op records in DXIL.td per the current design document. - Facilitate specification of overloads, shader stage and attributes predicated on DXIL Ops predicated DXIL version. Implement functionality to consume in TableGen backend, DXILEmitter, the above specification enhancements, and generate C++ code (in (DXILOperations.inc) that represents properties of DXIL Ops, associated type declarations and corresponding accessor functions. Changes to DXIL Op Lowering pass to consume the DXIL Op representation generated by the TableGen back end. Add mtriple with the required shader model version to commandline of tests.
26 lines
884 B
LLVM
26 lines
884 B
LLVM
; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
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; Make sure dxil operation function calls for isinf are generated for float and half.
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; CHECK: call i1 @dx.op.isSpecialFloat.f32(i32 9, float %{{.*}})
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; CHECK: call i1 @dx.op.isSpecialFloat.f16(i32 9, half %{{.*}})
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; Function Attrs: noinline nounwind optnone
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define noundef i1 @isinf_float(float noundef %a) #0 {
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entry:
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%a.addr = alloca float, align 4
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store float %a, ptr %a.addr, align 4
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%0 = load float, ptr %a.addr, align 4
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%dx.isinf = call i1 @llvm.dx.isinf.f32(float %0)
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ret i1 %dx.isinf
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}
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; Function Attrs: noinline nounwind optnone
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define noundef i1 @isinf_half(half noundef %p0) #0 {
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entry:
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%p0.addr = alloca half, align 2
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store half %p0, ptr %p0.addr, align 2
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%0 = load half, ptr %p0.addr, align 2
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%dx.isinf = call i1 @llvm.dx.isinf.f16(half %0)
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ret i1 %dx.isinf
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}
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