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llvm-project/llvm/test/CodeGen
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Jonathan Roelofs 17673ae0b2 [DAG] Fix PR45049: LegalizeTypes crash 
Sometimes LegalizeTypes knows about common subexpressions before SelectionDAG
does, leading to accidental SDValue removal before its reference count was
truly zero.

Fixes: https://bugs.llvm.org/show_bug.cgi?id=45049

https://reviews.llvm.org/D76994
2020-04-04 13:36:22 -06:00
..
AArch64
[AArch64] Fix swap-compare-operands test names to fix issue reported on D77354
2020-04-03 17:48:18 +01:00
AMDGPU
AMDGPU: Fix a few more tests with old denormal subtarget features
2020-04-03 23:42:13 -04:00
ARC
…
ARM
[NFC] Move ARM opt -indvars test from Codegen into Transforms
2020-04-03 20:15:03 +03:00
AVR
[AVR] Generalize the previous interrupt bugfix to signal handlers too
2020-03-31 19:33:34 +13:00
BPF
[BPF] support 128bit int explicitly in layout spec
2020-03-28 11:46:29 -07:00
Generic
[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
2020-03-26 14:10:20 -07:00
Hexagon
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
Inputs
…
Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[Mips] Make MipsBranchExpansion aware of BBIT family of branch
2020-03-31 09:20:51 +02:00
MIR
AMDGPU: Assume f32 denormals are enabled by default
2020-04-02 17:17:12 -04:00
MSP430
…
NVPTX
[DAGCombiner] Require ninf for sqrt recip estimation
2020-04-01 16:23:43 +08:00
PowerPC
[NFC][PowerPC] Pre-commit a test case for D77448
2020-04-03 20:43:04 -05:00
RISCV
[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
2020-04-01 15:51:26 +01:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.
2020-04-02 14:57:46 +02:00
Thumb
[DAGCombine] Skip PostInc combine with later users
2020-03-23 08:39:53 +00:00
Thumb2
[ARM] Fix incorrect handling of big-endian vmov.i64
2020-04-03 17:36:50 +01:00
VE
[VE] Target-specific bit size for sjljehprepare
2020-03-10 17:51:16 +01:00
WebAssembly
[WebAssembly] Fix wasm.lsda() optimization in WasmEHPrepare
2020-04-04 07:02:50 -07:00
WinCFGuard
…
WinEH
…
X86
[DAG] Fix PR45049: LegalizeTypes crash
2020-04-04 13:36:22 -06:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00