Luke Lau 971a4501f7 [RISCV] Model vlseg/vsseg in interleaved memory ops ...

If the legalized type is a legal interleaved access type (i.e. there's a
supported vlseg/vsseg instruction for it), the interleaved access pass
will pick any interleaved memory op (wide load + shuffles) and lower it
into a vlseg/vsseg intrinsic.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D146522

2023-04-04 15:05:14 +01:00

..

defaults.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

divrem.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

force-vect-msg.ll

[NFC] Port all runlines for LoopVectorize pass tests to -passes syntax

2022-12-05 22:17:30 +03:00

illegal-type.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

inloop-reduction.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

interleaved-accesses-zve32x.ll

[RISCV][NFC] Add tests for interleaved accesses in loop vectorizer

2023-03-09 17:43:16 +00:00

interleaved-accesses.ll

[RISCV] Model vlseg/vsseg in interleaved memory ops

2023-04-04 15:05:14 +01:00

interleaved-cost.ll

[RISCV] Model vlseg/vsseg in interleaved memory ops

2023-04-04 15:05:14 +01:00

lit.local.cfg

…

lmul.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

low-trip-count.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

mask-index-type.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

masked_gather_scatter.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

ordered-reduction.ll

[RISCV] Enable ordered reduction.

2023-03-07 04:36:50 -08:00

reg-usage.ll

[LV] Reland "Update logic for calculating register usage due to invariants"

2023-02-28 17:32:39 +05:30

riscv-interleaved.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

riscv-unroll.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

riscv-vector-reverse.ll

[LV] Reland "Update logic for calculating register usage due to invariants"

2023-02-28 17:32:39 +05:30

safe-dep-distance.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

scalable-basics.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

scalable-reductions.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

scalable-tailfold.ll

[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar tail

2023-03-24 09:43:50 +00:00

scalable-vf-hint.ll

[LoopVectorize] Convert some tests to opaque pointers (NFC)

2022-12-14 15:16:59 +01:00

select-cmp-reduction.ll

[AsmParser] Remove typed pointer auto-detection

2023-01-18 09:58:32 +01:00

short-trip-count.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00

strided-accesses.ll

Revert "[IVDescriptors] Add pointer InductionDescriptors with non-constant strides"

2023-03-31 11:08:50 +01:00

uniform-load-store.ll

[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar tail

2023-03-24 09:43:50 +00:00

unroll-in-loop-vectorizer.ll

[LoopVectorize] Convert some tests to opaque pointers (NFC)

2022-12-14 15:16:59 +01:00

zvl32b.ll

[RISCV] Increase default vectorizer LMUL to 2

2023-03-23 10:33:50 +00:00