The AArch64 backend, during lowering, will convert an 64bit vector insert to a
128bit vector:
vector_insert %dreg, %v, %idx
=>
%qreg = insert_subvector undef, %dreg, 0
%ins = vector_insert %qreg, %v, %idx
EXTRACT_SUBREG %ins, dsub
This creates a bit of mess in the DAG, and the EXTRACT_SUBREG being a machine
nodes makes it difficult to simplify. This patch removes that, treating the
64bit vector insert as legal and handling them with extra tablegen patterns.
The end result is a simpler DAG that is easier to write tablegen patterns for.
Differential Revision: https://reviews.llvm.org/D144550
18af853022