3717aa5ddb
The recent expression type changes still need more discussion, which will happen on phabricator or on the mailing list. The precise list of commits reverted are: - "Refactor division generation code" - "[NFC] Generate runtime checks after the SCoP" - "[FIX] Determine insertion point during SCEV expansion" - "Look through IntToPtr & PtrToInt instructions" - "Use minimal types for generated expressions" - "Temporarily promote values to i64 again" - "[NFC] Avoid unnecessary comparison for min/max expressions" - "[Polly] Fix -Wunused-variable warnings (NFC)" - "[NFC] Simplify min/max expression generation" - "Simplify the type adjustment in the IslExprBuilder" Some of them are just reverted as we would otherwise get conflicts. I will try to re-commit them if possible. llvm-svn: 272483
57 lines
2.9 KiB
LLVM
57 lines
2.9 KiB
LLVM
; RUN: opt %loadPolly -polly-opt-isl -polly-vectorizer=polly -polly-codegen < %s -S | FileCheck %s
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; #pragma known-parallel
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; for (int c0 = 0; c0 <= 31; c0 += 1)
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; for (int c1 = 0; c1 <= floord(nk - 1, 32); c1 += 1)
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; for (int c2 = 0; c2 <= 7; c2 += 1)
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; for (int c3 = 0; c3 <= min(31, nk - 32 * c1 - 1); c3 += 1)
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; #pragma simd
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; for (int c4 = 0; c4 <= 3; c4 += 1)
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; Stmt_for_body_3(32 * c0 + 4 * c2 + c4, 32 * c1 + c3);
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; CHECK: polly.stmt.for.body.3: ; preds = %polly.loop_header18
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; CHECK: %_p_splat_one = load <1 x double>, <1 x double>* %_p_vec_p, align 8, !alias.scope !1, !noalias !3, !llvm.mem.parallel_loop_access !0
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; CHECK: %_p_vec_full = load <4 x double>, <4 x double>* %vector_ptr, align 8, !alias.scope !4, !noalias !5, !llvm.mem.parallel_loop_access !0
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; CHECK: extractelement <4 x double> %addp_vec, i32 0
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; CHECK: extractelement <4 x double> %addp_vec, i32 1
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; CHECK: extractelement <4 x double> %addp_vec, i32 2
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; CHECK: extractelement <4 x double> %addp_vec, i32 3
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; CHECK: store <4 x double> %addp_vec, <4 x double>* {{.*}}, align 8, !alias.scope !4, !noalias !5, !llvm.mem.parallel_loop_access !0
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define void @kernel_gemm(i32 %ni, i32 %nj, i32 %nk, [1024 x double]* %C, [1024 x double]* %A) #0 {
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entry:
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br label %for.cond.1.preheader
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for.cond.1.preheader: ; preds = %entry, %for.inc.10
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%indvars.iv16 = phi i64 [ 0, %entry ], [ %indvars.iv.next17, %for.inc.10 ]
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%cmp2.13 = icmp sgt i32 %nk, 0
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br i1 %cmp2.13, label %for.body.3.lr.ph, label %for.inc.10
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for.body.3.lr.ph: ; preds = %for.cond.1.preheader
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br label %for.body.3
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for.body.3: ; preds = %for.body.3.lr.ph, %for.body.3
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%indvars.iv = phi i64 [ 0, %for.body.3.lr.ph ], [ %indvars.iv.next, %for.body.3 ]
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%arrayidx5 = getelementptr inbounds [1024 x double], [1024 x double]* %A, i64 0, i64 %indvars.iv
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%0 = load double, double* %arrayidx5, align 8
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%arrayidx9 = getelementptr inbounds [1024 x double], [1024 x double]* %C, i64 0, i64 %indvars.iv16
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%1 = load double, double* %arrayidx9, align 8
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%add = fadd double %0, %1
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store double %add, double* %arrayidx9, align 8
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp ne i32 %lftr.wideiv, %nk
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br i1 %exitcond, label %for.body.3, label %for.cond.1.for.inc.10_crit_edge
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for.cond.1.for.inc.10_crit_edge: ; preds = %for.body.3
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br label %for.inc.10
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for.inc.10: ; preds = %for.cond.1.for.inc.10_crit_edge, %for.cond.1.preheader
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%indvars.iv.next17 = add nuw nsw i64 %indvars.iv16, 1
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%exitcond18 = icmp ne i64 %indvars.iv.next17, 1024
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br i1 %exitcond18, label %for.cond.1.preheader, label %for.end.12
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for.end.12: ; preds = %for.inc.10
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ret void
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}
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