3bbe7a681e
Summary: This patch intends to support three most common relocation type on AIX: R_POS, R_TOC, R_RBR. These three relocation type will be needed for object file generation on AIX for small code model. We will have follow up patches to bring relocation support for large code model on AIX. Reviewers: hubert.reinterpretcast, daltenty, DiggerLin Differential Revision: https://reviews.llvm.org/D72027
77 lines
2.9 KiB
C++
77 lines
2.9 KiB
C++
//===-- PPCXCOFFObjectWriter.cpp - PowerPC XCOFF Writer -------------------===//
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//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCFixupKinds.h"
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "llvm/BinaryFormat/XCOFF.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/MC/MCXCOFFObjectWriter.h"
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using namespace llvm;
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namespace {
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class PPCXCOFFObjectWriter : public MCXCOFFObjectTargetWriter {
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static constexpr uint8_t SignBitMask = 0x80;
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public:
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PPCXCOFFObjectWriter(bool Is64Bit);
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std::pair<uint8_t, uint8_t>
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getRelocTypeAndSignSize(const MCValue &Target, const MCFixup &Fixup,
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bool IsPCRel) const override;
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};
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} // end anonymous namespace
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PPCXCOFFObjectWriter::PPCXCOFFObjectWriter(bool Is64Bit)
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: MCXCOFFObjectTargetWriter(Is64Bit) {}
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std::unique_ptr<MCObjectTargetWriter>
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llvm::createPPCXCOFFObjectWriter(bool Is64Bit) {
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return std::make_unique<PPCXCOFFObjectWriter>(Is64Bit);
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}
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std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize(
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const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const {
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const MCSymbolRefExpr::VariantKind Modifier =
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Target.isAbsolute() ? MCSymbolRefExpr::VK_None
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: Target.getSymA()->getKind();
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// People from AIX OS team says AIX link editor does not care about
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// the sign bit in the relocation entry "most" of the time.
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// The system assembler seems to set the sign bit on relocation entry
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// based on similar property of IsPCRel. So we will do the same here.
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// TODO: More investigation on how assembler decides to set the sign
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// bit, and we might want to match that.
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const uint8_t EncodedSignednessIndicator = IsPCRel ? SignBitMask : 0u;
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// The magic number we use in SignAndSize has a strong relationship with
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// the corresponding MCFixupKind. In most cases, it's the MCFixupKind
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// number - 1, because SignAndSize encodes the bit length being
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// relocated minus 1.
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switch ((unsigned)Fixup.getKind()) {
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default:
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report_fatal_error("Unimplemented fixup kind.");
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case PPC::fixup_ppc_half16:
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switch (Modifier) {
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default:
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report_fatal_error("Unsupported modifier for half16 fixup.");
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case MCSymbolRefExpr::VK_None:
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return {XCOFF::RelocationType::R_TOC, EncodedSignednessIndicator | 15};
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}
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break;
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case PPC::fixup_ppc_br24:
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// Branches are 4 byte aligned, so the 24 bits we encode in
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// the instruction actually represents a 26 bit offset.
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return {XCOFF::RelocationType::R_RBR, EncodedSignednessIndicator | 25};
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case FK_Data_4:
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return {XCOFF::RelocationType::R_POS, EncodedSignednessIndicator | 31};
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}
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}
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