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llvm-project/llvm/lib/Target/AArch64
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Cullen Rhodes 14cb138b15 [AArch64][SME] Update DUP (predicate) instruction 
Changes in architecture revision 00eac1:
  * Renamed to PSEL.
  * Copies whole source register.
  * Element type suffix removed from destination.
  * Element index no longer optional and '#' prefix has been removed.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-09

Depends on D111212.

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D111213
2021-10-07 08:55:11 +00:00
..
AsmParser
[AArch64][SME] Update tile slice index offset
2021-10-07 08:55:10 +00:00
Disassembler
[AArch64][SME] Update tile slice index offset
2021-10-07 08:55:10 +00:00
GISel
AArch64+GISel: legalize vector remainder operations.
2021-10-05 10:20:10 +01:00
MCTargetDesc
[AArch64][SME] Update tile slice index offset
2021-10-07 08:55:10 +00:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
[AArch64][SVE] Add API for conversion between SVE predicate pattern and element number. NFC
2021-08-27 20:03:48 +08:00
AArch64.h
Revert "Second Recommit "[AArch64] Split bitmask immediate of bitwise AND operation""
2021-10-06 08:39:48 +00:00
AArch64.td
[AArch64] Improve schedule modelling on the Cortex-A55
2021-09-21 13:03:34 +01:00
AArch64A53Fix835769.cpp
…
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
…
AArch64AsmPrinter.cpp
[MC] Add MCSubtargetInfo to MCAlignFragment
2021-09-07 15:46:19 +01:00
AArch64BranchTargets.cpp
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.
2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp
[clang][AArch64] Correctly align HFA arguments when passed on the stack
2021-04-15 22:58:14 +01:00
AArch64CallingConvention.h
…
AArch64CallingConvention.td
[AArch64] Replace unneeded CCAssignToRegWithShadow with CCAssignToReg
2021-08-21 16:33:29 -07:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
2021-03-01 13:52:57 -08:00
AArch64Combine.td
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
2021-10-01 15:01:20 -07:00
AArch64CompressJumpTables.cpp
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
2020-12-10 12:20:02 -08:00
AArch64CondBrTuning.cpp
…
AArch64ConditionalCompares.cpp
…
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
AArch64FalkorHWPFFix.cpp
…
AArch64FastISel.cpp
[Target] Migrate from getNumArgOperands to arg_size (NFC)
2021-10-02 12:06:29 -07:00
AArch64FrameLowering.cpp
Add a command-line flag to control the Swift extended async frame info.
2021-09-16 06:57:45 -07:00
AArch64FrameLowering.h
[NFC] Fix a few whitespace issues and typos.
2021-07-04 11:49:58 +01:00
AArch64GenRegisterBankInfo.def
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrAtomics.td
[AArch64] Fix i128 cmpxchg using ldxp/stxp.
2021-07-20 12:38:12 -07:00
AArch64InstrFormats.td
[AArch64][SME] Update tile slice index offset
2021-10-07 08:55:10 +00:00
AArch64InstrGISel.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64InstrInfo.cpp
[MachineOutliner][AArch64] Ensure LR is live-in when inserting reg-save calls
2021-09-08 17:44:27 -07:00
AArch64InstrInfo.h
[InstrInfo] Use 64-bit immediates for analyzeCompare() (NFCI)
2021-08-30 19:46:04 +02:00
AArch64InstrInfo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64ISelDAGToDAG.cpp
[APInt] Stop using soft-deprecated constructors and methods in llvm. NFC.
2021-10-04 08:57:44 +01:00
AArch64ISelLowering.cpp
[APInt] Stop using soft-deprecated constructors and methods in llvm. NFC.
2021-10-04 08:57:44 +01:00
AArch64ISelLowering.h
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
2021-09-20 09:50:11 +01:00
AArch64LoadStoreOptimizer.cpp
AArch64: don't form indexed paired ops if base reg overlaps operands.
2021-08-20 11:39:38 +01:00
AArch64LowerHomogeneousPrologEpilog.cpp
[CodeGen] Add missing includes (NFC)
2021-06-06 15:48:27 +02:00
AArch64MachineFunctionInfo.cpp
[llvm] Rename StringRef _lower() method calls to _insensitive()
2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h
IR/AArch64/X86: add "swifttailcc" calling convention.
2021-05-17 10:48:34 +01:00
AArch64MacroFusion.cpp
[AArch64] Fix some coding standard issues related to namespace llvm
2021-05-05 15:27:16 -07:00
AArch64MacroFusion.h
[llvm] Add missing header guards (NFC)
2021-01-30 09:53:42 -08:00
AArch64MCInstLower.cpp
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
2021-05-07 09:44:26 -07:00
AArch64MCInstLower.h
…
AArch64PBQPRegAlloc.cpp
[NFCI] Move DEBUG_TYPE definition below #includes
2021-05-30 17:31:01 +08:00
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
…
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
[AArch64] Fix Copy Elemination for negative values
2020-12-18 13:30:46 +00:00
AArch64RegisterBanks.td
AArch64: support i128 cmpxchg in GlobalISel.
2021-05-14 10:41:38 +01:00
AArch64RegisterInfo.cpp
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
AArch64RegisterInfo.h
Change materializeFrameBaseRegister() to return register
2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td
[AArch64][SVE] NFC: Remove unused p0-p7 with element size predicates
2021-08-10 07:56:22 +00:00
AArch64SchedA53.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA55.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA57.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedA57WriteRes.td
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
2021-01-04 10:58:43 +00:00
AArch64SchedA64FX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedCyclone.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM3.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM4.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedExynosM5.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkor.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedFalkorDetails.td
…
AArch64SchedKryo.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedKryoDetails.td
…
AArch64SchedPredExynos.td
…
AArch64SchedPredicates.td
…
AArch64SchedThunderX2T99.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedThunderX3T110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedThunderX.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SchedTSV110.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64Schedule.td
[AArch64] Model Cortex-A55 Q register NEON instructions
2021-09-29 16:55:31 +01:00
AArch64SelectionDAGInfo.cpp
[SelectionDAG] Add isZero/isAllOnes methods to ConstantSDNode.
2021-09-09 13:28:30 -07:00
AArch64SelectionDAGInfo.h
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
2021-02-18 16:55:16 +00:00
AArch64SIMDInstrOpt.cpp
…
AArch64SLSHardening.cpp
[ARM][AArch64] SLSHardening: make non-comdat thunks possible
2021-05-20 17:07:05 +02:00
AArch64SMEInstrInfo.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
AArch64SpeculationHardening.cpp
…
AArch64StackTagging.cpp
[hwasan] Support more complicated lifetimes.
2021-09-03 10:29:50 +01:00
AArch64StackTaggingPreRA.cpp
[llvm] Use pop_back_val (NFC)
2021-09-19 13:44:23 -07:00
AArch64StorePairSuppress.cpp
[AArch64] Disable AArch64StorePairSuppress under optsize
2021-10-04 18:28:15 +01:00
AArch64Subtarget.cpp
[AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
2021-06-21 13:00:36 +01:00
AArch64Subtarget.h
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
2021-09-20 09:50:11 +01:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Fix extract_subvector patterns for unpacked fp types.
2021-09-29 11:14:49 +01:00
AArch64SystemOperands.td
[AArch64][MC] Merge FeaturePMU into FeaturePerfMon
2021-09-06 14:56:49 +01:00
AArch64TargetMachine.cpp
Revert "Second Recommit "[AArch64] Split bitmask immediate of bitwise AND operation""
2021-10-06 08:39:48 +00:00
AArch64TargetMachine.h
…
AArch64TargetObjectFile.cpp
…
AArch64TargetObjectFile.h
…
AArch64TargetTransformInfo.cpp
[AArch64][SVE] Propagate math flags from intrinsics to instructions
2021-10-05 15:39:13 +01:00
AArch64TargetTransformInfo.h
[Target][CodeGen] Remove default CostKind arguments on inner/impl TTI overrides
2021-09-22 15:28:08 +01:00
CMakeLists.txt
Revert "Second Recommit "[AArch64] Split bitmask immediate of bitwise AND operation""
2021-10-06 08:39:48 +00:00
SMEInstrFormats.td
[AArch64][SME] Update DUP (predicate) instruction
2021-10-07 08:55:11 +00:00
SVEInstrFormats.td
[AArch64][SVE] Remove redundant PTEST following PNEXT/PFIRST
2021-10-05 15:10:48 +00:00
SVEIntrinsicOpts.cpp
[llvm][clang][NFC] updates inline licence info
2021-08-11 02:48:53 +00:00