7d39a8a921
Add the tail policy argument to LLVM IR intrinsics. There are two policies for tail elements. Tail agnostic means users do not care about the values in the tail elements and tail undisturbed means the values in the tail elements need to be kept after the operation. In order to let users control the tail policy, we add an additional argument at the end of the argument list. For unmasked operations, we have no maskedoff and the tail policy is always tail agnostic. If users want to keep tail elements under unmasked operations, they could use all one mask in the masked operations to do it. So, we only add the additional argument for masked operations for most cases. There are exceptions listed below. In this patch, we do not handle the following cases to reduce the complexity of the patch. There could be two separate patches for them. * Use dest argument to control tail policy vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest argument) vfmerge.vfm (add _t builtins with additional dest argument) vmv.v.v (add _t builtins with additional dest argument) vmv.v.x (add _t builtins with additional dest argument) vmv.v.i (add _t builtins with additional dest argument) vfmv.v.f (add _t builtins with additional dest argument) vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest argument) vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument) * Always has tail argument for masked/unmasked intrinsics Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt builtins) Vector Widening Integer Multiply-Add Instructions (add _t and _mt builtins) Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins) Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins) Vector Reduction Operations (add _t and _mt builtins) Vector Slideup Instructions (add _t and _mt builtins) Vector Slidedown Instructions (add _t and _mt builtins) Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101 Differential Revision: https://reviews.llvm.org/D105092
44 lines
2.2 KiB
LLVM
44 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64-unknown-unknown-elf"
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define dso_local <16 x i16> @interleave(<8 x i16> %v0, <8 x i16> %v1) {
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; CHECK-LABEL: interleave:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v26, v9
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; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8m2
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
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; CHECK-NEXT: vmv.v.i v28, 0
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; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu
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; CHECK-NEXT: vmv2r.v v30, v28
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; CHECK-NEXT: vslideup.vi v30, v8, 0
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu
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; CHECK-NEXT: vslideup.vi v30, v8, 8
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vsrl.vi v12, v10, 1
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; CHECK-NEXT: vrgather.vv v14, v30, v12
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; CHECK-NEXT: vsetivli zero, 8, e16, m2, tu, mu
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; CHECK-NEXT: vslideup.vi v28, v26, 0
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, tu, mu
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; CHECK-NEXT: vslideup.vi v28, v8, 8
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu
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; CHECK-NEXT: vrgather.vv v8, v14, v10
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; CHECK-NEXT: lui a0, 11
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; CHECK-NEXT: addiw a0, a0, -1366
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; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
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; CHECK-NEXT: vrgather.vv v8, v28, v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
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%v3 = shufflevector <8 x i16> %v1, <8 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%v4 = shufflevector <16 x i16> %v2, <16 x i16> %v3, <16 x i32> <i32 0, i32 16, i32 2, i32 17, i32 4, i32 18, i32 6, i32 19, i32 8, i32 20, i32 10, i32 21, i32 12, i32 22, i32 14, i32 23>
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ret <16 x i16> %v4
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}
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