a825fb2c07
This change combines for ROCm what was done for CUDA in D97463, D98203, D98360, and D98396. I did not try to compile SerializeToHsaco.cpp or test mlir/test/Integration/GPU/ROCM because I don't have an AMD card. I fixed the things that had obvious bit-rot though. Reviewed By: whchung Differential Revision: https://reviews.llvm.org/D98447
94 lines
3.1 KiB
MLIR
94 lines
3.1 KiB
MLIR
// RUN: mlir-opt %s \
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// RUN: -convert-scf-to-std \
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// RUN: -gpu-kernel-outlining \
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// RUN: -pass-pipeline='gpu.module(strip-debuginfo,convert-gpu-to-rocdl,gpu-to-hsaco)' \
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// RUN: -gpu-to-llvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%linalg_test_lib_dir/libmlir_rocm_runtime%shlibext \
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// RUN: --shared-libs=%linalg_test_lib_dir/libmlir_runner_utils%shlibext \
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// RUN: --entry-point-result=void \
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// RUN: | FileCheck %s
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func @vectransferx2(%arg0 : memref<?xf32>, %arg1 : memref<?xf32>) {
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%cst = constant 1 : index
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gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %cst, %grid_y = %cst, %grid_z = %cst)
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threads(%tx, %ty, %tz) in (%block_x = %cst, %block_y = %cst, %block_z = %cst) {
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%f0 = constant 0.0: f32
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%base = constant 0 : index
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%f = vector.transfer_read %arg0[%base], %f0
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{permutation_map = affine_map<(d0) -> (d0)>} :
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memref<?xf32>, vector<2xf32>
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%c = addf %f, %f : vector<2xf32>
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%base1 = constant 1 : index
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vector.transfer_write %c, %arg1[%base1]
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{permutation_map = affine_map<(d0) -> (d0)>} :
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vector<2xf32>, memref<?xf32>
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gpu.terminator
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}
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return
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}
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func @vectransferx4(%arg0 : memref<?xf32>, %arg1 : memref<?xf32>) {
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%cst = constant 1 : index
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gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %cst, %grid_y = %cst, %grid_z = %cst)
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threads(%tx, %ty, %tz) in (%block_x = %cst, %block_y = %cst, %block_z = %cst) {
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%f0 = constant 0.0: f32
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%base = constant 0 : index
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%f = vector.transfer_read %arg0[%base], %f0
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{permutation_map = affine_map<(d0) -> (d0)>} :
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memref<?xf32>, vector<4xf32>
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%c = addf %f, %f : vector<4xf32>
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vector.transfer_write %c, %arg1[%base]
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{permutation_map = affine_map<(d0) -> (d0)>} :
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vector<4xf32>, memref<?xf32>
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gpu.terminator
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}
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return
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}
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func @main() {
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%c0 = constant 0 : index
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%c1 = constant 1 : index
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%c4 = constant 4 : index
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%cf1 = constant 1.0 : f32
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%cf1dot23 = constant 1.23 : f32
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%arg0 = alloc() : memref<4xf32>
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%arg1 = alloc() : memref<4xf32>
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%22 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
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%23 = memref_cast %arg1 : memref<4xf32> to memref<?xf32>
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scf.for %i = %c0 to %c4 step %c1 {
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store %cf1dot23, %22[%i] : memref<?xf32>
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store %cf1dot23, %23[%i] : memref<?xf32>
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}
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%cast0 = memref_cast %22 : memref<?xf32> to memref<*xf32>
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%cast1 = memref_cast %23 : memref<?xf32> to memref<*xf32>
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gpu.host_register %cast0 : memref<*xf32>
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gpu.host_register %cast1 : memref<*xf32>
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%24 = call @mgpuMemGetDeviceMemRef1dFloat(%22) : (memref<?xf32>) -> (memref<?xf32>)
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%26 = call @mgpuMemGetDeviceMemRef1dFloat(%23) : (memref<?xf32>) -> (memref<?xf32>)
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// CHECK: [1.23, 2.46, 2.46, 1.23]
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call @vectransferx2(%24, %26) : (memref<?xf32>, memref<?xf32>) -> ()
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call @print_memref_f32(%cast1) : (memref<*xf32>) -> ()
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// CHECK: [2.46, 2.46, 2.46, 2.46]
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call @vectransferx4(%24, %26) : (memref<?xf32>, memref<?xf32>) -> ()
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call @print_memref_f32(%cast1) : (memref<*xf32>) -> ()
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return
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}
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func private @mgpuMemGetDeviceMemRef1dFloat(%ptr : memref<?xf32>) -> (memref<?xf32>)
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func private @print_memref_f32(%ptr : memref<*xf32>)
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