1c5d3a056c
Summary: This commit is the first step in rebasing all of BOLT history in the LLVM monorepo. It also solves trivial build issues by updating BOLT codebase to use current LLVM. There is still work left in rebasing some BOLT features and in making sure everything is working as intended. History has been rewritten to put BOLT in the /bolt folder, as opposed to /tools/llvm-bolt. (cherry picked from FBD33289252)
478 lines
15 KiB
C++
478 lines
15 KiB
C++
//===- MCPlusBuilder.cpp - main interface for MCPlus-level instructions ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Create/analyze/modify instructions at MC+ level.
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//
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//===----------------------------------------------------------------------===//
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#include "MCPlus.h"
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#include "MCPlusBuilder.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include <cstdint>
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#include <queue>
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#define DEBUG_TYPE "mcplus"
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using namespace llvm;
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using namespace bolt;
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using namespace MCPlus;
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bool MCPlusBuilder::equals(const MCInst &A, const MCInst &B,
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CompFuncTy Comp) const {
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if (A.getOpcode() != B.getOpcode())
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return false;
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unsigned NumOperands = MCPlus::getNumPrimeOperands(A);
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if (NumOperands != MCPlus::getNumPrimeOperands(B))
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return false;
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for (unsigned Index = 0; Index < NumOperands; ++Index) {
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if (!equals(A.getOperand(Index), B.getOperand(Index), Comp))
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return false;
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}
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return true;
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}
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bool MCPlusBuilder::equals(const MCOperand &A, const MCOperand &B,
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CompFuncTy Comp) const {
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if (A.isReg()) {
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if (!B.isReg())
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return false;
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return A.getReg() == B.getReg();
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} else if (A.isImm()) {
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if (!B.isImm())
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return false;
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return A.getImm() == B.getImm();
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} else if (A.isSFPImm()) {
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if (!B.isSFPImm())
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return false;
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return A.getSFPImm() == B.getSFPImm();
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} else if (A.isDFPImm()) {
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if (!B.isDFPImm())
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return false;
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return A.getDFPImm() == B.getDFPImm();
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} else if (A.isExpr()) {
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if (!B.isExpr())
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return false;
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return equals(*A.getExpr(), *B.getExpr(), Comp);
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} else {
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llvm_unreachable("unexpected operand kind");
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return false;
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}
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}
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bool MCPlusBuilder::equals(const MCExpr &A, const MCExpr &B,
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CompFuncTy Comp) const {
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if (A.getKind() != B.getKind())
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return false;
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switch (A.getKind()) {
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case MCExpr::Constant: {
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const auto &ConstA = cast<MCConstantExpr>(A);
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const auto &ConstB = cast<MCConstantExpr>(B);
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return ConstA.getValue() == ConstB.getValue();
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}
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case MCExpr::SymbolRef: {
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const MCSymbolRefExpr &SymbolA = cast<MCSymbolRefExpr>(A);
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const MCSymbolRefExpr &SymbolB = cast<MCSymbolRefExpr>(B);
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return SymbolA.getKind() == SymbolB.getKind() &&
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Comp(&SymbolA.getSymbol(), &SymbolB.getSymbol());
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}
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case MCExpr::Unary: {
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const auto &UnaryA = cast<MCUnaryExpr>(A);
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const auto &UnaryB = cast<MCUnaryExpr>(B);
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return UnaryA.getOpcode() == UnaryB.getOpcode() &&
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equals(*UnaryA.getSubExpr(), *UnaryB.getSubExpr(), Comp);
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}
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case MCExpr::Binary: {
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const auto &BinaryA = cast<MCBinaryExpr>(A);
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const auto &BinaryB = cast<MCBinaryExpr>(B);
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return BinaryA.getOpcode() == BinaryB.getOpcode() &&
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equals(*BinaryA.getLHS(), *BinaryB.getLHS(), Comp) &&
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equals(*BinaryA.getRHS(), *BinaryB.getRHS(), Comp);
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}
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case MCExpr::Target: {
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const auto &TargetExprA = cast<MCTargetExpr>(A);
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const auto &TargetExprB = cast<MCTargetExpr>(B);
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return equals(TargetExprA, TargetExprB, Comp);
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}
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}
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llvm_unreachable("Invalid expression kind!");
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}
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bool MCPlusBuilder::equals(const MCTargetExpr &A, const MCTargetExpr &B,
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CompFuncTy Comp) const {
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llvm_unreachable("target-specific expressions are unsupported");
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}
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Optional<MCLandingPad> MCPlusBuilder::getEHInfo(const MCInst &Inst) const {
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if (!isCall(Inst))
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return NoneType();
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auto LPSym = getAnnotationOpValue(Inst, MCAnnotation::kEHLandingPad);
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if (!LPSym)
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return NoneType();
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auto Action = getAnnotationOpValue(Inst, MCAnnotation::kEHAction);
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if (!Action)
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return NoneType();
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return std::make_pair(reinterpret_cast<const MCSymbol *>(*LPSym),
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static_cast<uint64_t>(*Action));
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}
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void MCPlusBuilder::addEHInfo(MCInst &Inst, const MCLandingPad &LP) {
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if (isCall(Inst)) {
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assert(!getEHInfo(Inst));
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setAnnotationOpValue(Inst, MCAnnotation::kEHLandingPad,
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reinterpret_cast<int64_t>(LP.first));
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setAnnotationOpValue(Inst, MCAnnotation::kEHAction,
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static_cast<int64_t>(LP.second));
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}
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}
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int64_t MCPlusBuilder::getGnuArgsSize(const MCInst &Inst) const {
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auto Value = getAnnotationOpValue(Inst, MCAnnotation::kGnuArgsSize);
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if (!Value)
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return -1LL;
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return *Value;
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}
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void MCPlusBuilder::addGnuArgsSize(MCInst &Inst, int64_t GnuArgsSize,
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AllocatorIdTy AllocId) {
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assert(GnuArgsSize >= 0 && "cannot set GNU_args_size to negative value");
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assert(getGnuArgsSize(Inst) == -1LL && "GNU_args_size already set");
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assert(isInvoke(Inst) && "GNU_args_size can only be set for invoke");
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setAnnotationOpValue(Inst, MCAnnotation::kGnuArgsSize, GnuArgsSize, AllocId);
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}
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uint64_t MCPlusBuilder::getJumpTable(const MCInst &Inst) const {
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auto Value = getAnnotationOpValue(Inst, MCAnnotation::kJumpTable);
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if (!Value)
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return 0;
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return *Value;
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}
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uint16_t MCPlusBuilder::getJumpTableIndexReg(const MCInst &Inst) const {
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return getAnnotationAs<uint16_t>(Inst, "JTIndexReg");
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}
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bool MCPlusBuilder::setJumpTable(MCInst &Inst, uint64_t Value,
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uint16_t IndexReg, AllocatorIdTy AllocId) {
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if (!isIndirectBranch(Inst))
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return false;
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setAnnotationOpValue(Inst, MCAnnotation::kJumpTable, Value, AllocId);
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getOrCreateAnnotationAs<uint16_t>(Inst, "JTIndexReg", AllocId) = IndexReg;
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return true;
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}
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bool MCPlusBuilder::unsetJumpTable(MCInst &Inst) {
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if (!getJumpTable(Inst))
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return false;
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removeAnnotation(Inst, MCAnnotation::kJumpTable);
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removeAnnotation(Inst, "JTIndexReg");
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return true;
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}
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Optional<uint64_t>
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MCPlusBuilder::getConditionalTailCall(const MCInst &Inst) const {
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auto Value = getAnnotationOpValue(Inst, MCAnnotation::kConditionalTailCall);
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if (!Value)
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return NoneType();
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return static_cast<uint64_t>(*Value);
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}
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bool
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MCPlusBuilder::setConditionalTailCall(MCInst &Inst, uint64_t Dest) {
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if (!isConditionalBranch(Inst))
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return false;
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setAnnotationOpValue(Inst, MCAnnotation::kConditionalTailCall, Dest);
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return true;
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}
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bool MCPlusBuilder::unsetConditionalTailCall(MCInst &Inst) {
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if (!getConditionalTailCall(Inst))
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return false;
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removeAnnotation(Inst, MCAnnotation::kConditionalTailCall);
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return true;
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}
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bool MCPlusBuilder::hasAnnotation(const MCInst &Inst, unsigned Index) const {
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const auto *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return false;
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return (bool)getAnnotationOpValue(Inst, Index);
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}
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bool MCPlusBuilder::removeAnnotation(MCInst &Inst, unsigned Index) {
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auto *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return false;
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for (int I = AnnotationInst->getNumOperands() - 1; I >= 0; --I) {
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auto ImmValue = AnnotationInst->getOperand(I).getImm();
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if (extractAnnotationIndex(ImmValue) == Index) {
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AnnotationInst->erase(AnnotationInst->begin() + I);
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return true;
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}
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}
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return false;
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}
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void MCPlusBuilder::stripAnnotations(MCInst &Inst, bool KeepTC) {
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auto *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return;
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// Preserve TailCall annotation.
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auto IsTCOrErr = tryGetAnnotationAs<bool>(Inst, "TC");
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Inst.erase(std::prev(Inst.end()));
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if (KeepTC && IsTCOrErr)
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addAnnotation(Inst, "TC", *IsTCOrErr);
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}
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void
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MCPlusBuilder::printAnnotations(const MCInst &Inst, raw_ostream &OS) const {
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const auto *AnnotationInst = getAnnotationInst(Inst);
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if (!AnnotationInst)
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return;
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for (unsigned I = 0; I < AnnotationInst->getNumOperands(); ++I) {
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const auto Imm = AnnotationInst->getOperand(I).getImm();
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const auto Index = extractAnnotationIndex(Imm);
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const auto Value = extractAnnotationValue(Imm);
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const auto *Annotation =
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reinterpret_cast<const MCAnnotation *>(Value);
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if (Index >= MCAnnotation::kGeneric) {
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OS << " # " << AnnotationNames[Index - MCAnnotation::kGeneric]
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<< ": ";
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Annotation->print(OS);
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}
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}
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}
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bool MCPlusBuilder::evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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return Analysis->evaluateBranch(Inst, Addr, Size, Target);
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}
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void MCPlusBuilder::getClobberedRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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}
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const auto &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getTouchedRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/false);
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}
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const auto *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/false);
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}
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/false);
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}
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}
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void MCPlusBuilder::getWrittenRegs(const MCInst &Inst,
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BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitDefs = InstInfo.getImplicitDefs();
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for (unsigned I = 0, E = InstInfo.getNumImplicitDefs(); I != E; ++I) {
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Regs |= getAliases(ImplicitDefs[I], /*OnlySmaller=*/true);
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}
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for (unsigned I = 0, E = InstInfo.getNumDefs(); I != E; ++I) {
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const auto &Operand = Inst.getOperand(I);
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assert(Operand.isReg());
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Regs |= getAliases(Operand.getReg(), /*OnlySmaller=*/true);
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}
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}
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void MCPlusBuilder::getUsedRegs(const MCInst &Inst, BitVector &Regs) const {
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if (isPrefix(Inst) || isCFI(Inst))
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return;
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const auto &InstInfo = Info->get(Inst.getOpcode());
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const auto *ImplicitUses = InstInfo.getImplicitUses();
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for (unsigned I = 0, E = InstInfo.getNumImplicitUses(); I != E; ++I) {
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Regs |= getAliases(ImplicitUses[I], /*OnlySmaller=*/true);
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}
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for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
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if (!Inst.getOperand(I).isReg())
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continue;
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Regs |= getAliases(Inst.getOperand(I).getReg(), /*OnlySmaller=*/true);
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}
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}
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bool MCPlusBuilder::hasDefOfPhysReg(const MCInst &MI, unsigned Reg) const {
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const auto &InstInfo = Info->get(MI.getOpcode());
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return InstInfo.hasDefOfPhysReg(MI, Reg, *RegInfo);
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}
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bool MCPlusBuilder::hasUseOfPhysReg(const MCInst &MI, unsigned Reg) const {
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const auto &InstInfo = Info->get(MI.getOpcode());
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for (int I = InstInfo.NumDefs; I < InstInfo.NumOperands; ++I)
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if (MI.getOperand(I).isReg() &&
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RegInfo->isSubRegisterEq(Reg, MI.getOperand(I).getReg()))
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return true;
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if (const uint16_t *ImpUses = InstInfo.ImplicitUses)
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for (; *ImpUses; ++ImpUses)
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if (*ImpUses == Reg || RegInfo->isSubRegister(Reg, *ImpUses))
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return true;
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return false;
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}
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const BitVector &
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MCPlusBuilder::getAliases(MCPhysReg Reg,
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bool OnlySmaller) const {
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// AliasMap caches a mapping of registers to the set of registers that
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// alias (are sub or superregs of itself, including itself).
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static std::vector<BitVector> AliasMap;
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static std::vector<MCPhysReg> SuperReg;
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if (AliasMap.size() > 0) {
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if (OnlySmaller)
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return AliasMap[Reg];
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return AliasMap[SuperReg[Reg]];
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}
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// Build alias map
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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BitVector BV(RegInfo->getNumRegs(), false);
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BV.set(I);
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AliasMap.emplace_back(std::move(BV));
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SuperReg.emplace_back(I);
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}
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std::queue<MCPhysReg> Worklist;
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// Propagate alias info upwards. Skip reg 0 (mapped to NoRegister)
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for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I) {
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Worklist.push(I);
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}
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while (!Worklist.empty()) {
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MCPhysReg I = Worklist.front();
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Worklist.pop();
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for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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AliasMap[I] |= AliasMap[*SI];
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}
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for (MCSuperRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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Worklist.push(*SI);
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}
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}
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// Propagate parent reg downwards
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for (MCPhysReg I = 1, E = RegInfo->getNumRegs(); I < E; ++I) {
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Worklist.push(I);
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}
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while (!Worklist.empty()) {
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MCPhysReg I = Worklist.front();
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Worklist.pop();
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for (MCSubRegIterator SI(I, RegInfo); SI.isValid(); ++SI) {
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SuperReg[*SI] = SuperReg[I];
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Worklist.push(*SI);
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}
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}
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LLVM_DEBUG({
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dbgs() << "Dumping reg alias table:\n";
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for (MCPhysReg I = 0, E = RegInfo->getNumRegs(); I != E; ++I) {
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dbgs() << "Reg " << I << ": ";
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const BitVector &BV = AliasMap[SuperReg[I]];
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int Idx = BV.find_first();
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while (Idx != -1) {
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dbgs() << Idx << " ";
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Idx = BV.find_next(Idx);
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}
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dbgs() << "\n";
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}
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});
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if (OnlySmaller)
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return AliasMap[Reg];
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return AliasMap[SuperReg[Reg]];
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}
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uint8_t
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MCPlusBuilder::getRegSize(MCPhysReg Reg) const {
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// SizeMap caches a mapping of registers to their sizes
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static std::vector<uint8_t> SizeMap;
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if (SizeMap.size() > 0) {
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return SizeMap[Reg];
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}
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SizeMap = std::vector<uint8_t>(RegInfo->getNumRegs());
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// Build size map
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for (auto I = RegInfo->regclass_begin(), E = RegInfo->regclass_end(); I != E;
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++I) {
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for (MCPhysReg Reg : *I) {
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SizeMap[Reg] = I->getSizeInBits() / 8;
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}
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}
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return SizeMap[Reg];
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}
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bool MCPlusBuilder::setOperandToSymbolRef(MCInst &Inst, int OpNum,
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const MCSymbol *Symbol,
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int64_t Addend, MCContext *Ctx,
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uint64_t RelType) const {
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MCOperand Operand;
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if (!Addend) {
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Operand = MCOperand::createExpr(getTargetExprFor(
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Inst, MCSymbolRefExpr::create(Symbol, *Ctx), *Ctx, RelType));
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} else {
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Operand = MCOperand::createExpr(getTargetExprFor(
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Inst,
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MCBinaryExpr::createAdd(MCSymbolRefExpr::create(Symbol, *Ctx),
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MCConstantExpr::create(Addend, *Ctx), *Ctx),
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*Ctx, RelType));
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}
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Inst.getOperand(OpNum) = Operand;
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return true;
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}
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